1 095d0ed3 2024-10-05 benni INTEL 80286 PROGRAMMER'S REFERENCE MANUAL 1987
3 095d0ed3 2024-10-05 benni Intel Corporation makes no warranty for the use of its products and
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17 095d0ed3 2024-10-05 benni ICE, iCEL, iCS, iDBP, iDIS, I²ICE, iLBX, im, iMDDX, iMMX, Inboard, Insite,
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20 095d0ed3 2024-10-05 benni iSXM, KEPROM, Library Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME,
21 095d0ed3 2024-10-05 benni MULTIBUS, MULTICHANNEL, MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP,
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31 095d0ed3 2024-10-05 benni *MULTIBUS is a patented Intel bus.
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42 095d0ed3 2024-10-05 benni (c)INTEL CORPORATION 1987 CG-10/86
47 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────────────────────────────
50 095d0ed3 2024-10-05 benni This manual describes the 80286, the most powerful 16-bit microprocessor in
51 095d0ed3 2024-10-05 benni the 8086 family, and the 80287 Numeric Processor Extension (NPX).
53 095d0ed3 2024-10-05 benni Organization of This Manual
57 095d0ed3 2024-10-05 benni The 80286 contains a table of contents, eleven chapters, four appendices,
58 095d0ed3 2024-10-05 benni and an index. For more information on the 80286 book's organization, see its
59 095d0ed3 2024-10-05 benni first chapter, Chapter 1, "Introduction to the 80286." Section 1.4 in that
60 095d0ed3 2024-10-05 benni chapter explains the organization in detail.
62 095d0ed3 2024-10-05 benni Notational Conventions
63 095d0ed3 2024-10-05 benni This manual uses special notation to represent sub- and superscript
64 095d0ed3 2024-10-05 benni characters. Subscript characters are surrounded by {curly brackets}, for
65 095d0ed3 2024-10-05 benni example 10{2} = 10 base 2. Superscript characters are preceeded by a caret
66 095d0ed3 2024-10-05 benni and enclosed within (parentheses), for example 10^(3) = 10 to the third
69 095d0ed3 2024-10-05 benni Table of Contents
71 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────────────────────────────
74 095d0ed3 2024-10-05 benni Chapter 1 Introduction to the 80286
76 095d0ed3 2024-10-05 benni 1.1 General Attributes
77 095d0ed3 2024-10-05 benni 1.2 Modes of Operation
78 095d0ed3 2024-10-05 benni 1.3 Advanced Features
79 095d0ed3 2024-10-05 benni 1.3.1 Memory Management
80 095d0ed3 2024-10-05 benni 1.3.2 Task Management
81 095d0ed3 2024-10-05 benni 1.3.3 Protection Mechanisms
82 095d0ed3 2024-10-05 benni 1.3.4 Support for Operating Systems
84 095d0ed3 2024-10-05 benni 1.4 Organization of This Book
85 095d0ed3 2024-10-05 benni 1.5 Related Publications
87 095d0ed3 2024-10-05 benni Chapter 2 80286 Base Architecture
89 095d0ed3 2024-10-05 benni 2.1 Memory Organization and Segmentation
90 095d0ed3 2024-10-05 benni 2.2 Data Types
91 095d0ed3 2024-10-05 benni 2.3 Registers
92 095d0ed3 2024-10-05 benni 2.3.1 General Registers
93 095d0ed3 2024-10-05 benni 2.3.2 Memory Segmentation and Segment Registers
94 095d0ed3 2024-10-05 benni 2.3.3 Index, Pointer, and Base Registers
95 095d0ed3 2024-10-05 benni 2.3.4 Status and Control Registers
97 095d0ed3 2024-10-05 benni 2.4 Addressing Modes
98 095d0ed3 2024-10-05 benni 2.4.1 Operands
99 095d0ed3 2024-10-05 benni 2.4.2 Register and Immediate Modes
100 095d0ed3 2024-10-05 benni 2.4.3 Memory Addressing Modes
101 095d0ed3 2024-10-05 benni 2.4.3.1 Segment Selection
102 095d0ed3 2024-10-05 benni 2.4.3.2 Offset Computation
103 095d0ed3 2024-10-05 benni 2.4.3.3 Memory Mode
105 095d0ed3 2024-10-05 benni 2.5 Input/Output
106 095d0ed3 2024-10-05 benni 2.5.1 I/O Address Space
107 095d0ed3 2024-10-05 benni 2.5.2 Memory-Mapped I\0
109 095d0ed3 2024-10-05 benni 2.6 Interrupts and Exceptions
110 095d0ed3 2024-10-05 benni 2.7 Hierarchy of Instruction Sets
112 095d0ed3 2024-10-05 benni Chapter 3 Basic Instruction Set
114 095d0ed3 2024-10-05 benni 3.1 Data Movement Instructions
115 095d0ed3 2024-10-05 benni 3.1.1 General-Purpose Data Movement Instructions
116 095d0ed3 2024-10-05 benni 3.1.2 Stack Manipulation Instructions
118 095d0ed3 2024-10-05 benni 3.2 Flag Operation with the Basic Instruction Set
119 095d0ed3 2024-10-05 benni 3.2.1 Status Flags 4
120 095d0ed3 2024-10-05 benni 3.2.2 Control Flags 4
122 095d0ed3 2024-10-05 benni 3.3 Arithmetic Instructions
123 095d0ed3 2024-10-05 benni 3.3.1 Addition Instructions
124 095d0ed3 2024-10-05 benni 3.3.2 Subtraction Instructions
125 095d0ed3 2024-10-05 benni 3.3.3 Muitiplication Instructions
126 095d0ed3 2024-10-05 benni 3.3.4 Division Instructions
128 095d0ed3 2024-10-05 benni 3.4 Logical Instructions
129 095d0ed3 2024-10-05 benni 3.4.1 Boolean Operation Instructions
130 095d0ed3 2024-10-05 benni 3.4.2 Shift and Rotate Instructions
131 095d0ed3 2024-10-05 benni 3.4.2.1 Shift Instructions
132 095d0ed3 2024-10-05 benni 3.4.2.2 Rotate Instructions
134 095d0ed3 2024-10-05 benni 3.4.3 Type Conversion and No-Operation Instructions
136 095d0ed3 2024-10-05 benni 3.5 Test and Compare Instructions
137 095d0ed3 2024-10-05 benni 3.6 Control Transfer Instructions
138 095d0ed3 2024-10-05 benni 3.6.1 Unconditional Transfer Instructions
139 095d0ed3 2024-10-05 benni 3.6.1.1 Jump instruction
140 095d0ed3 2024-10-05 benni 3.6.1.2 Call Instruction
141 095d0ed3 2024-10-05 benni 3.6.1.3 Return and Return from interrupt Instruction
143 095d0ed3 2024-10-05 benni 3.6.2 Conditional Transfer Instructions
144 095d0ed3 2024-10-05 benni 3.6.2.1 Conditional Jump Instructions
145 095d0ed3 2024-10-05 benni 3.6.2.2 Loop Instructions
146 095d0ed3 2024-10-05 benni 3.6.2.3 Executing a Loop or Repeat Zero Times
148 095d0ed3 2024-10-05 benni 3.6.3 Software-Generated Interrupts
149 095d0ed3 2024-10-05 benni 3.6.3.1 Software Interrupt Instruction
151 095d0ed3 2024-10-05 benni 3.7 Character Translation and String Instructions
152 095d0ed3 2024-10-05 benni 3.7.1 Translate Instruction
153 095d0ed3 2024-10-05 benni 3.7.2 String Manipulation Instructions and Repeat Prefixes
154 095d0ed3 2024-10-05 benni 3.7.2.1 String Movement Instructions
155 095d0ed3 2024-10-05 benni 3.7.2.2 Other String Operations
157 095d0ed3 2024-10-05 benni 3.8 Address Manipulation Instructions
158 095d0ed3 2024-10-05 benni 3.9 Flag Control instructions
159 095d0ed3 2024-10-05 benni 3.9.1 Carry Flag Control Instructions
160 095d0ed3 2024-10-05 benni 3.9.2 Direction Flag Control Instructions
161 095d0ed3 2024-10-05 benni 3.9.3 Flag Transfer Instructions
163 095d0ed3 2024-10-05 benni 3.10 Binary-Coded Decimal Arithmetic Instructions
164 095d0ed3 2024-10-05 benni 3.10.1 Packed BCD Adjustment Instructions
165 095d0ed3 2024-10-05 benni 3.10.2 Unpacked BCD Adjustment Instructions
167 095d0ed3 2024-10-05 benni 3.11 Trusted Instructions
168 095d0ed3 2024-10-05 benni 3.11.1 Trusted and Privileged Restrictions on POPF and IRET
169 095d0ed3 2024-10-05 benni 3.11.2 Machine State Instructions
170 095d0ed3 2024-10-05 benni 3.11.3 Inputand Output Instructions
172 095d0ed3 2024-10-05 benni 3.12 Processor Extension Instructions
173 095d0ed3 2024-10-05 benni 3.12.1 Processor Extension Synchronization Instructions
174 095d0ed3 2024-10-05 benni 3.12.2 Numeric Data Processor Instructions
175 095d0ed3 2024-10-05 benni 3.12.2.1 Arithmetic Instructions
176 095d0ed3 2024-10-05 benni 3.12.2.2 Comparison Instructions
177 095d0ed3 2024-10-05 benni 3.12.2.3 Transcendental Instructions
178 095d0ed3 2024-10-05 benni 3.12.2.4 Data Transfer Instructions
179 095d0ed3 2024-10-05 benni 3.12.2.5 Constant Instructions
181 095d0ed3 2024-10-05 benni Chapter 4 Extended Instruction Set
183 095d0ed3 2024-10-05 benni 4.1 Block I\O Instructions
184 095d0ed3 2024-10-05 benni 4.2 High-Level Instructions
186 095d0ed3 2024-10-05 benni Chapter 5 Real Address Mode
188 095d0ed3 2024-10-05 benni 5.1 Addressing and Segmentation
189 095d0ed3 2024-10-05 benni 5.2 Interrupt Handling
190 095d0ed3 2024-10-05 benni 5.2.1 Interrupt Vector Table
191 095d0ed3 2024-10-05 benni 5.2.1.1 Interrupt Procedures
192 095d0ed3 2024-10-05 benni 5.2.2 Interrupt Priorities
193 095d0ed3 2024-10-05 benni 5.2.3 Reserved and Dedicated Interrupt Vectors
195 095d0ed3 2024-10-05 benni 5.3 System Initialization.
197 095d0ed3 2024-10-05 benni Chapter 6 Memory Management and Virtual Addressing
199 095d0ed3 2024-10-05 benni 6.1 Memory Management Overview
200 095d0ed3 2024-10-05 benni 6.2 Virtual Addresses
201 095d0ed3 2024-10-05 benni 6.3 Descriptor Tables
202 095d0ed3 2024-10-05 benni 6.4 Virtual-to-Physical Address Translation
203 095d0ed3 2024-10-05 benni 6.5 Segments and Segment Descriptors
204 095d0ed3 2024-10-05 benni 6.6 Memory Management Registers
205 095d0ed3 2024-10-05 benni 6.6.1 Segment Address Translation Registers
206 095d0ed3 2024-10-05 benni 6.6.2 System Address Registers
208 095d0ed3 2024-10-05 benni Chapter 7 Protection
210 095d0ed3 2024-10-05 benni 7.1 Introduction
211 095d0ed3 2024-10-05 benni 7.1.1 Types of Protection
212 095d0ed3 2024-10-05 benni 7.1.2 Protection Implementation
214 095d0ed3 2024-10-05 benni 7.2 Memory Management and Protection
215 095d0ed3 2024-10-05 benni 7.2.1 Separation of Address Spaces
216 095d0ed3 2024-10-05 benni 7.2.2 LDT and GDT Access Checks
217 095d0ed3 2024-10-05 benni 7.2.3 Type Validation
219 095d0ed3 2024-10-05 benni 7.3 Privilege Levels and Protection
220 095d0ed3 2024-10-05 benni 7.3.1 Example of Using Four Privilege Levels
221 095d0ed3 2024-10-05 benni 7.3.2 Privilege Usage
223 095d0ed3 2024-10-05 benni 7.4 Segment Descriptor
224 095d0ed3 2024-10-05 benni 7.4.1 Data Accesses
225 095d0ed3 2024-10-05 benni 7.4.2 Code Segment Access
226 095d0ed3 2024-10-05 benni 7.4.3 Data Access Restriction by Privilege Level
227 095d0ed3 2024-10-05 benni 7.4.4 Pointer Privilege Stamping via ARPL
229 095d0ed3 2024-10-05 benni 7.5 Control Transfers
230 095d0ed3 2024-10-05 benni 7.5.1 Gates
231 095d0ed3 2024-10-05 benni 7.5.1.1 Call Gates
232 095d0ed3 2024-10-05 benni 7.5.1.2 Intra-Level Transfers via Call Gate
233 095d0ed3 2024-10-05 benni 7.5.1.3 Inter-Level Control Transfer via Call Gates
234 095d0ed3 2024-10-05 benni 7.5.1.4 Stack Changes Caused by Call Gates
236 095d0ed3 2024-10-05 benni 7.5.2 Inter-Level Returns
238 095d0ed3 2024-10-05 benni Chapter 8 Tasks and State Transitions
240 095d0ed3 2024-10-05 benni 8.1 Introduction
241 095d0ed3 2024-10-05 benni 8.2 Task State Segments and Descriptors
242 095d0ed3 2024-10-05 benni 8.2.1 Task State Segment Descriptors
244 095d0ed3 2024-10-05 benni 8.3 Task Switching
245 095d0ed3 2024-10-05 benni 8.4 Task Linking
246 095d0ed3 2024-10-05 benni 8.5 Task Gates
248 095d0ed3 2024-10-05 benni Chapter 9 Interrupts and Exceptions
250 095d0ed3 2024-10-05 benni 9.1 Interrupt Descriptor Table
251 095d0ed3 2024-10-05 benni 9.2 Hardware Initiated Interrupts
252 095d0ed3 2024-10-05 benni 9.3 Software Initiated Interrupts
253 095d0ed3 2024-10-05 benni 9.4 Interrupt Gates and Trap Gates
254 095d0ed3 2024-10-05 benni 9.5 Task Gates and Interrupt Tasks
255 095d0ed3 2024-10-05 benni 9.5.1 Scheduling Considerations
256 095d0ed3 2024-10-05 benni 9.5.2 Deciding Between Task, Trap, and Interrupt Gates
258 095d0ed3 2024-10-05 benni 9.6 Protection Exceptions and Reserved Vectors
259 095d0ed3 2024-10-05 benni 9.6.1 Invalid OP-Code (Interrupt 6)
260 095d0ed3 2024-10-05 benni 9.6.2 Double Fault (Interrupt 8)
261 095d0ed3 2024-10-05 benni 9.6.3 Processor Extension Segment Overrun (Interrupt 9)
262 095d0ed3 2024-10-05 benni 9.6.4 Invalid Task State Segment (Interrupt 10)
263 095d0ed3 2024-10-05 benni 9.6.5 Not Present (Interrupt 11)
264 095d0ed3 2024-10-05 benni 9.6.6 Stack Fault (Interrupt 12)
265 095d0ed3 2024-10-05 benni 9.6.7 General Protection Fault (Interrupt 13)
267 095d0ed3 2024-10-05 benni 9.7 Additional Exceptions and Interrupts
268 095d0ed3 2024-10-05 benni 9.7.1 Single Step Interrupt (Interrupt 1)
270 095d0ed3 2024-10-05 benni Chapter 10 System Control and Initialization
272 095d0ed3 2024-10-05 benni 10.1 System Flags and Registers
273 095d0ed3 2024-10-05 benni 10.1.1 Descriptor Table Registers
275 095d0ed3 2024-10-05 benni 10.2 System Control Instructions
276 095d0ed3 2024-10-05 benni 10.2.1 Machine Status Word
277 095d0ed3 2024-10-05 benni 10.2.2 Other Instructions
279 095d0ed3 2024-10-05 benni 10.3 Privileged and Trusted Instructions
281 095d0ed3 2024-10-05 benni 10.4 Initialization
282 095d0ed3 2024-10-05 benni 10.4.1 Real Address Mode
283 095d0ed3 2024-10-05 benni 10.4.2 Protected Mode
285 095d0ed3 2024-10-05 benni Chapter 11 Advanced Topics
287 095d0ed3 2024-10-05 benni 11.1 Virtual Memory Management
288 095d0ed3 2024-10-05 benni 11.2 Special Segment Attributes
289 095d0ed3 2024-10-05 benni 11.2.1 Conforming Code Segments
290 095d0ed3 2024-10-05 benni 11.2.2 Expand-Down Data Segments
292 095d0ed3 2024-10-05 benni 11.3 Pointer Validation
293 095d0ed3 2024-10-05 benni 11.3.1 Descriptor Validation
294 095d0ed3 2024-10-05 benni 11.3.2 Pointer Integrity: RPL and the"Trojan Horse Problem"
296 095d0ed3 2024-10-05 benni 11.4 NPX Context Switching
297 095d0ed3 2024-10-05 benni 11.5 Multiprocessor Considerations
298 095d0ed3 2024-10-05 benni 11.6 Shutdown
300 095d0ed3 2024-10-05 benni Appendix A 80286 System Initialization
302 095d0ed3 2024-10-05 benni Appendix B The 80286 Instruction Set
304 095d0ed3 2024-10-05 benni Appendix C 8086/8088 Compatibility Considerations
306 095d0ed3 2024-10-05 benni Appendix D 80286/80386 Software Compatibility Considerations
312 095d0ed3 2024-10-05 benni 1-1 Four Privilege Levels
314 095d0ed3 2024-10-05 benni 2-1 Segmented Virtual Memory
315 095d0ed3 2024-10-05 benni 2-2 Bytes and Words in Memory.
316 095d0ed3 2024-10-05 benni 2-3 80286/80287 Supported Data Types
317 095d0ed3 2024-10-05 benni 2-4 80286 Base Architecture Register Set
318 095d0ed3 2024-10-05 benni 2-5 Real Address Mode Segment Selector Interpretation
319 095d0ed3 2024-10-05 benni 2-6 Protected Mode Segment Selector Interpretation
320 095d0ed3 2024-10-05 benni 2-7 80286 Stack
321 095d0ed3 2024-10-05 benni 2-8 Stack Operation
322 095d0ed3 2024-10-05 benni 2-9 BP Usage as a Stack Frame Base Pointer
323 095d0ed3 2024-10-05 benni 2-10 Flags Register.
324 095d0ed3 2024-10-05 benni 2-11 Two-Component Address
325 095d0ed3 2024-10-05 benni 2-12 Use of Memory Segmentation
326 095d0ed3 2024-10-05 benni 2-13 Complex Addressing Modes
327 095d0ed3 2024-10-05 benni 2-14 Memory-Mapped I/O
328 095d0ed3 2024-10-05 benni 2-15 Hierarchy of Instructions
334 095d0ed3 2024-10-05 benni 3-5 Flag Word Contents
335 095d0ed3 2024-10-05 benni 3-6 SAL and SHL
342 095d0ed3 2024-10-05 benni 3-13 LAHF and SAHF
343 095d0ed3 2024-10-05 benni 3-14 PUSHF and POPF
345 095d0ed3 2024-10-05 benni 4-1 Formal Definition of the ENTER Instruction
346 095d0ed3 2024-10-05 benni 4-2 Variable Access in Nested Procedures
347 095d0ed3 2024-10-05 benni 4-2a Stack Frame for MAIN at Level 1
348 095d0ed3 2024-10-05 benni 4-2b Stack Frame for Procedure A
349 095d0ed3 2024-10-05 benni 4-2c Stack Frame for Procedure B at Level 3 Called from A
350 095d0ed3 2024-10-05 benni 4-2d Stack Frame for Procedure C at Level 3 Called from B
352 095d0ed3 2024-10-05 benni 5-1a Forming the Segment Base Address
353 095d0ed3 2024-10-05 benni 5-1b Forming the 20-Bit Physical Address in the Real Address Mode
354 095d0ed3 2024-10-05 benni 5-2 Overlapping Segments to Save Physical Memory
355 095d0ed3 2024-10-05 benni 5-3 Interrupt Vector Table for Real Address Mode
356 095d0ed3 2024-10-05 benni 5-4 Stack Structure after Interrupt (Real Address Mode)
358 095d0ed3 2024-10-05 benni 6-1 Format of the Segment Selector Component
359 095d0ed3 2024-10-05 benni 6-2 Address Spaces and Task Isolation
360 095d0ed3 2024-10-05 benni 6-3 Segment Descriptor (S=1)
361 095d0ed3 2024-10-05 benni 6-4 Special Purpose Descriptors or System Segment Descriptors (S=O)
362 095d0ed3 2024-10-05 benni 6-5 LDT Descriptor
363 095d0ed3 2024-10-05 benni 6-6 Virtual-to-Physical Address Translation
364 095d0ed3 2024-10-05 benni 6-7 Segment Descriptor Access Bytes
365 095d0ed3 2024-10-05 benni 6-8 Memory Management Registers
366 095d0ed3 2024-10-05 benni 6-9 Descriptor Loading
368 095d0ed3 2024-10-05 benni 7-1 Addressing Segments of a Module within a Task
369 095d0ed3 2024-10-05 benni 7-2 Descriptor Cache Registers
370 095d0ed3 2024-10-05 benni 7-3 80286 Virtual Address Space
371 095d0ed3 2024-10-05 benni 7-4 Local and Global Descriptor Table Definitions
372 095d0ed3 2024-10-05 benni 7-5 Error Code Format (on the stack)
373 095d0ed3 2024-10-05 benni 7-6 Code and Data Segments Assigned to a Privilege Level.
374 095d0ed3 2024-10-05 benni 7-7 Selector Fields
375 095d0ed3 2024-10-05 benni 7-8 Access Byte Examples.
376 095d0ed3 2024-10-05 benni 7-9 Pointer Privilege Stamping
377 095d0ed3 2024-10-05 benni 7-10 Gate Descriptor Format.
378 095d0ed3 2024-10-05 benni 7-11 Call Gate
379 095d0ed3 2024-10-05 benni 7-12 Stack Contents after an Inter-Level Call
381 095d0ed3 2024-10-05 benni 8-1 Task State Segment and TSS Registers
382 095d0ed3 2024-10-05 benni 8-2 TSS Descriptor
383 095d0ed3 2024-10-05 benni 8-3 Task Gate Descriptor
384 095d0ed3 2024-10-05 benni 8-4 Task Switch Through a Task Gate
386 095d0ed3 2024-10-05 benni 9-1 Interrupt Descriptor Table Definition
387 095d0ed3 2024-10-05 benni 9-2 IDT Selector Error Code.
388 095d0ed3 2024-10-05 benni 9-3 Trap/Interrupt Gate Descriptors
389 095d0ed3 2024-10-05 benni 9-4 Stack Layout after an Exception with an Error Code
391 095d0ed3 2024-10-05 benni 10-1 Local and Global Descriptor Table Definition
392 095d0ed3 2024-10-05 benni 10-2 Interrupt Descriptor Table Definition
393 095d0ed3 2024-10-05 benni 10-3 Data Type for Global Descriptor Table and Interrupt Descriptor Table
395 095d0ed3 2024-10-05 benni 11-1 Expand-Down Segment
396 095d0ed3 2024-10-05 benni 11-2 Dynamic Segment Relocation and Expansion of Segment Limit
397 095d0ed3 2024-10-05 benni 11-3 Example of NPX Context Switching
399 095d0ed3 2024-10-05 benni B-1 /n Instruction Byte Format
400 095d0ed3 2024-10-05 benni B-2 /r Instruction Byte Format
404 095d0ed3 2024-10-05 benni 2-1 Implied Segment Usage by Index, Pointer, and Base Registers
405 095d0ed3 2024-10-05 benni 2-2 Segment Register Selection Rules
406 095d0ed3 2024-10-05 benni 2-3 Memory Operand Addressing Modes
407 095d0ed3 2024-10-05 benni 2-4 80286 Interrupt Vector Assignments (Real Address Mode)
409 095d0ed3 2024-10-05 benni 3-1 Status Flags' Functions
410 095d0ed3 2024-10-05 benni 3-2 Control Flags' Functions
411 095d0ed3 2024-10-05 benni 3-3 Interpretation of Conditional Transfers
413 095d0ed3 2024-10-05 benni 5-1 Interrupt Processing Order
414 095d0ed3 2024-10-05 benni 5-2 Dedicated and Reserved Interrupt Vectors in Real Address Mode
415 095d0ed3 2024-10-05 benni 5-3 Processor State after RESET
417 095d0ed3 2024-10-05 benni 7-1 Segment Access Rights Byte Format
418 095d0ed3 2024-10-05 benni 7-2 Allowed Segment Types in Segment Registers
419 095d0ed3 2024-10-05 benni 7-3 Call Gate Checks
420 095d0ed3 2024-10-05 benni 7-4 Inter-Level Return Checks
422 095d0ed3 2024-10-05 benni 8-1 Checks Made during a Task Switch
423 095d0ed3 2024-10-05 benni 8-2 Effect of a Task Switch on BUSY and NT Bits and the Link Word
425 095d0ed3 2024-10-05 benni 9-1 Trap and Interrupt Gate Checks
426 095d0ed3 2024-10-05 benni 9-2 Interrupt and Gate Interactions
427 095d0ed3 2024-10-05 benni 9-3 Reserved Exceptions and Interrupts
428 095d0ed3 2024-10-05 benni 9-4 Interrupt Processing Order
429 095d0ed3 2024-10-05 benni 9-5 Conditions That Invalidate the TSS
431 095d0ed3 2024-10-05 benni 10-1 MSW Bit Functions
432 095d0ed3 2024-10-05 benni 10-2 Recommended MSW Encodings for Processor Extension Control
434 095d0ed3 2024-10-05 benni 11-1 NPX Context Switching
436 095d0ed3 2024-10-05 benni B-1 ModRM Values
437 095d0ed3 2024-10-05 benni B-2 Protection Exceptions of the 80286
438 095d0ed3 2024-10-05 benni B-3 Hexadecimal Values for the Access Rights Byte
440 095d0ed3 2024-10-05 benni C-1 New 80286 Interrupts
444 095d0ed3 2024-10-05 benni Chapter 1 Introduction to the 80286
446 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
448 095d0ed3 2024-10-05 benni The 80286 is the most powerful 16-bit processor in the 8086 series of
449 095d0ed3 2024-10-05 benni microprocessors, which includes the 8086, the 8088, the 80186, the 80188,
450 095d0ed3 2024-10-05 benni and the 80286. It is designed for applications that require very high
451 095d0ed3 2024-10-05 benni performance. It is also an excellent choice for sophisticated "high end"
452 095d0ed3 2024-10-05 benni applications that will benefit from its advanced architectural features:
453 095d0ed3 2024-10-05 benni memory management, protection mechanisms, task management, and virtual
454 095d0ed3 2024-10-05 benni memory support. The 80286 provides, on a single VLSI chip, computational
455 095d0ed3 2024-10-05 benni and architectural characteristics normally associated with much larger
456 095d0ed3 2024-10-05 benni minicomputers.
458 095d0ed3 2024-10-05 benni Sections 1.1, 1.2, and 1.3 of this chapter provide an overview of the 80286
459 095d0ed3 2024-10-05 benni architecture. Because the 80286 represents an extension of the 8086
460 095d0ed3 2024-10-05 benni architecture, some of this overview material may be new and unfamiliar to
461 095d0ed3 2024-10-05 benni previous users of the 8086 and similar microprocessors. But the 80286 is
462 095d0ed3 2024-10-05 benni also an evolutionary development, with the new architecture superimposed
463 095d0ed3 2024-10-05 benni upon the industry standard 8086 in such a way as to affect only the design
464 095d0ed3 2024-10-05 benni and programming of operating systems and other such system software.
465 095d0ed3 2024-10-05 benni Section 1.4 of this chapter provides a guide to the organization of this
466 095d0ed3 2024-10-05 benni manual, suggesting which chapters are relevant to the needs of particular
470 095d0ed3 2024-10-05 benni 1.1 General Attributes
472 095d0ed3 2024-10-05 benni The 80286 base architecture has many features in common with the
473 095d0ed3 2024-10-05 benni architecture of other members of the 8086 family, such as byte addressable
474 095d0ed3 2024-10-05 benni memory, I/O interfacing hardware, interrupt vectoring, and support for both
475 095d0ed3 2024-10-05 benni multiprocessing and processor extensions. The entire family has a common
476 095d0ed3 2024-10-05 benni set of addressing modes and basic instructions. The 80286 base architecture
477 095d0ed3 2024-10-05 benni also includes a number of extensions which add to the versatility of the
480 095d0ed3 2024-10-05 benni The 80286 processor can function in two modes of operation (see section 1.2
481 095d0ed3 2024-10-05 benni of this chapter, Modes of Operation). In one of these modes only the base
482 095d0ed3 2024-10-05 benni architecture is available to programmers, whereas in the other mode a number
483 095d0ed3 2024-10-05 benni of very powerful advanced features have been added, including support for
484 095d0ed3 2024-10-05 benni virtual memory, multitasking, and a sophisticated protection mechanism.
485 095d0ed3 2024-10-05 benni These advanced features are described in section 1.3 of this chapter.
487 095d0ed3 2024-10-05 benni The 80286 base architecture was designed to support programming in
488 095d0ed3 2024-10-05 benni high-level languages, such as Pascal, C or PL/M. The register set and
489 095d0ed3 2024-10-05 benni instructions are well suited to compiler-generated code. The addressing
490 095d0ed3 2024-10-05 benni modes (see section 2.4.3 in Chapter 2) allow efficient addressing
491 095d0ed3 2024-10-05 benni of complex data structures, such as static and dynamic arrays, records,
492 095d0ed3 2024-10-05 benni and arrays within records, which are commonly supported by high-level
493 095d0ed3 2024-10-05 benni languages. The data types supported by the architecture include, along with
494 095d0ed3 2024-10-05 benni bytes and words, high level language constructs such as strings, BCD, and
495 095d0ed3 2024-10-05 benni floating point.
497 095d0ed3 2024-10-05 benni The memory architecture of the 80286 was designed to support modular
498 095d0ed3 2024-10-05 benni programming techniques. Memory is divided into segments, which may be of
499 095d0ed3 2024-10-05 benni arbitrary size, that can be used to contain procedures and data structures.
500 095d0ed3 2024-10-05 benni Segmentation has several advantages over more conventional linear memory
501 095d0ed3 2024-10-05 benni architectures. It supports structured software, since segments can contain
502 095d0ed3 2024-10-05 benni meaningful program units and data, and more compact code, since references
503 095d0ed3 2024-10-05 benni within a segment can be shorter (and locality of reference usually insures
504 095d0ed3 2024-10-05 benni that the next few references will be within the same segment). Segmentation
505 095d0ed3 2024-10-05 benni also lends itself to efficient implementation of sophisticated memory
506 095d0ed3 2024-10-05 benni management, virtual memory, and memory protection.
508 095d0ed3 2024-10-05 benni In addition, new instructions have been added to the base architecture to
509 095d0ed3 2024-10-05 benni give hardware support for procedure invocations, parameter passing, and
510 095d0ed3 2024-10-05 benni array bounds checking.
513 095d0ed3 2024-10-05 benni 1.2 Modes of Operation
515 095d0ed3 2024-10-05 benni The 80286 can be operated in either of two different modes: Real Address
516 095d0ed3 2024-10-05 benni Mode or Protected Virtual Address Mode (also referred to as Protected Mode).
517 095d0ed3 2024-10-05 benni In either mode of operation, the 80286 represents an upwardly compatible
518 095d0ed3 2024-10-05 benni addition to the 8086 family of processors.
520 095d0ed3 2024-10-05 benni In Real Address Mode, the 80286 operates essentially as a very
521 095d0ed3 2024-10-05 benni high-performance 8086. Programs written for the 8086 or the 80186 can be
522 095d0ed3 2024-10-05 benni executed in this mode without any modification (the few exceptions are
523 095d0ed3 2024-10-05 benni described in Appendix C, "Compatibility Considerations"). Such upward
524 095d0ed3 2024-10-05 benni compatibility extends even to the object code level; for example, an 8086
525 095d0ed3 2024-10-05 benni program stored in read-only memory will execute successfully in 80286 Real
526 095d0ed3 2024-10-05 benni Address Mode. An 80286 operating in Real Address Mode provides a number of
527 095d0ed3 2024-10-05 benni instructions not found on the 8086. These additional instructions, also
528 095d0ed3 2024-10-05 benni present with the 80186, allow for efficient subroutine linkage, parameter
529 095d0ed3 2024-10-05 benni validation, index calculations, and block I/O transfers.
531 095d0ed3 2024-10-05 benni The advanced architectural features and full capabilities of the 80286 are
532 095d0ed3 2024-10-05 benni realized in its native Protected Mode. Among these features are
533 095d0ed3 2024-10-05 benni sophisticated mechanisms to support data protection, system integrity, task
534 095d0ed3 2024-10-05 benni concurrency, and memory management, including virtual storage.
535 095d0ed3 2024-10-05 benni Nevertheless, even in Protected Mode, the 80286 remains upwardly compatible
536 095d0ed3 2024-10-05 benni with most 8086 and 80186 application programs. Most 8086 applications
537 095d0ed3 2024-10-05 benni programs can be re-compiled or re-assembled and executed on the 80286 in
538 095d0ed3 2024-10-05 benni Protected Mode.
541 095d0ed3 2024-10-05 benni 1.3 Advanced Features
543 095d0ed3 2024-10-05 benni The architectural features described in section 1.1 of this chapter
544 095d0ed3 2024-10-05 benni are common to both operating modes of the processor. In addition to these
545 095d0ed3 2024-10-05 benni common features, Protected Mode provides a number of advanced features,
546 095d0ed3 2024-10-05 benni including a greatly extended physical and logical address space, new
547 095d0ed3 2024-10-05 benni instructions, and support for additional hardware-recognized data
548 095d0ed3 2024-10-05 benni structures. The Protected Mode 80286 includes a sophisticated memory
549 095d0ed3 2024-10-05 benni management and multilevel protection mechanism. Full hardware support is
550 095d0ed3 2024-10-05 benni included for multitasking and task switching operations.
553 095d0ed3 2024-10-05 benni 1.3.1 Memory Management
555 095d0ed3 2024-10-05 benni The memory architecture of the Protected Mode 80286 represents a
556 095d0ed3 2024-10-05 benni significant advance over that of the 8086. The physical address space has
557 095d0ed3 2024-10-05 benni been increased from 1 megabyte to 16 megabytes (2^(24) bytes), while the
558 095d0ed3 2024-10-05 benni virtual address space (i.e., the address space visible to a program) has
559 095d0ed3 2024-10-05 benni been increased from 1 megabyte to 1 gigabyte (2^(30) bytes). Moreover,
560 095d0ed3 2024-10-05 benni separate virtual address spaces are provided for each task in a
561 095d0ed3 2024-10-05 benni multi-tasking system (see the next section, 1.3.2, "Task Management").
563 095d0ed3 2024-10-05 benni The 80286 supports on-chip memory management instead of relying on an
564 095d0ed3 2024-10-05 benni external memory management unit. The one-chip solution is preferable because
565 095d0ed3 2024-10-05 benni no software is required to manage an external memory management unit,
566 095d0ed3 2024-10-05 benni performance is much better, and hardware designs are significantly simpler.
568 095d0ed3 2024-10-05 benni Mechanisms have been included in the 80286 architecture to allow the
569 095d0ed3 2024-10-05 benni efficient implementation of virtual memory systems. (In virtual memory
570 095d0ed3 2024-10-05 benni systems, the user regards the combination of main and external storage as a
571 095d0ed3 2024-10-05 benni single large memory. The user can write large programs without worrying
572 095d0ed3 2024-10-05 benni about the physical memory limitations of the system. To accomplish this, the
573 095d0ed3 2024-10-05 benni operating system places some of the user programs and data in external
574 095d0ed3 2024-10-05 benni storage and brings them into main memory only as they are needed.) All
575 095d0ed3 2024-10-05 benni instructions that can cause a segment-not-present fault are fully
576 095d0ed3 2024-10-05 benni restartable. Thus, a not-present segment can be loaded from external
577 095d0ed3 2024-10-05 benni storage, and the task can be restarted at the point where the fault
580 095d0ed3 2024-10-05 benni The 80286, like all members of the 8086 series, supports a segmented memory
581 095d0ed3 2024-10-05 benni architecture. The 80286 also fully integrates memory segmentation into a
582 095d0ed3 2024-10-05 benni comprehensive protection scheme. This protection scheme includes
583 095d0ed3 2024-10-05 benni hardware-enforced length and type checking to protect segments from
584 095d0ed3 2024-10-05 benni inadvertent misuse.
587 095d0ed3 2024-10-05 benni 1.3.2 Task Management
589 095d0ed3 2024-10-05 benni The 80286 is designed to support multi-tasking systems. The architecture
590 095d0ed3 2024-10-05 benni provides direct support for the concept of a task. For example, task state
591 095d0ed3 2024-10-05 benni segments (see section 8.2 in Chapter 8) are hardware-recognized and
592 095d0ed3 2024-10-05 benni hardware-manipulated structures that contain information on the current
593 095d0ed3 2024-10-05 benni state of all tasks in the system.
595 095d0ed3 2024-10-05 benni Very efficient context-switching (task-switching) can be invoked with a
596 095d0ed3 2024-10-05 benni single instruction. Separate logical address spaces are provided for each
597 095d0ed3 2024-10-05 benni task in the system. Finally, mechanisms exist to support intertask
598 095d0ed3 2024-10-05 benni communication, synchronization, memory sharing, and task scheduling. Task
599 095d0ed3 2024-10-05 benni Management is described in Chapter 8.
602 095d0ed3 2024-10-05 benni 1.3.3 Protection Mechanisms
604 095d0ed3 2024-10-05 benni The 80286 allows the system designer to define a comprehensive protection
605 095d0ed3 2024-10-05 benni policy to be applied, uniformly and continuously, to all ongoing operations
606 095d0ed3 2024-10-05 benni of the system. Such a policy may be desirable to ensure system reliability,
607 095d0ed3 2024-10-05 benni privacy of data, rapid error recovery, and separation of multiple users.
609 095d0ed3 2024-10-05 benni The 80286 protection mechanisms are based on the notion of a "hierarchy of
610 095d0ed3 2024-10-05 benni trust." Four privilege levels are distinguished, ranging from Level 0 (most
611 095d0ed3 2024-10-05 benni trusted) to Level 3 (least trusted). Level 0 is usually reserved for the
612 095d0ed3 2024-10-05 benni operating system kernel. The four levels may be visualized as concentric
613 095d0ed3 2024-10-05 benni rings, with the most privileged level in the center (see figure 1-1).
615 095d0ed3 2024-10-05 benni This four-level scheme offers system reliability, flexibility, and design
616 095d0ed3 2024-10-05 benni options not possible with the typical two-level (supervisor/user) separation
617 095d0ed3 2024-10-05 benni provided by other processors. A four-level division is capable of separating
618 095d0ed3 2024-10-05 benni kernel, executive, system services, and application software, each with
619 095d0ed3 2024-10-05 benni different privileges.
621 095d0ed3 2024-10-05 benni At any one time, a task executes at one of the four levels. Moreover, all
622 095d0ed3 2024-10-05 benni data segments and code segments are also assigned to privilege levels. A
623 095d0ed3 2024-10-05 benni task executing at one level cannot access data at a more privileged level,
624 095d0ed3 2024-10-05 benni nor can it call a procedure at a less privileged level (i.e., trust a less
625 095d0ed3 2024-10-05 benni privileged procedure to do work for it). Thus, both access to data and
626 095d0ed3 2024-10-05 benni transfer of control are restricted in appropriate ways.
628 095d0ed3 2024-10-05 benni A complete separation can exist between the logical address spaces local to
629 095d0ed3 2024-10-05 benni different tasks, providing users with automatic protection against
630 095d0ed3 2024-10-05 benni accidental or malicious interference by other users. The hardware also
631 095d0ed3 2024-10-05 benni provides immediate detection of a number of fault and error conditions, a
632 095d0ed3 2024-10-05 benni feature that can be useful in the development and maintenance of software.
634 095d0ed3 2024-10-05 benni Finally, these protection mechanisms require relatively little system
635 095d0ed3 2024-10-05 benni overhead because they are integrated into the memory management and
636 095d0ed3 2024-10-05 benni protection hardware of the processor itself.
639 095d0ed3 2024-10-05 benni Figure 1-1. Four Privilege Levels
641 095d0ed3 2024-10-05 benni ╔═══════════════════════════╗
642 095d0ed3 2024-10-05 benni ║ LEVEL 3 ◄────────╫──LEAST TRUSTED
643 095d0ed3 2024-10-05 benni ║ ╔═════════════════════╗ ║
644 095d0ed3 2024-10-05 benni ║ ║ LEVEL 2 ║ ║
645 095d0ed3 2024-10-05 benni ║ ║ ╔═══════════════╗ ║ ║
646 095d0ed3 2024-10-05 benni ║ ║ ║ LEVEL 1 ║ ║ ║
647 095d0ed3 2024-10-05 benni ║ ║ ║ ╔═════════╗ ║ ║ ║
648 095d0ed3 2024-10-05 benni ║ ║ ║ ║ LEVEL 0 ║ ║ ║ ║
649 095d0ed3 2024-10-05 benni ║ ║ ║ ║ ▲ ║ ║ ║ ║
650 095d0ed3 2024-10-05 benni ║ ║ ║ ╚═══════╪═╝ ║ ║ ║
651 095d0ed3 2024-10-05 benni ║ ║ ║ │ ║ ║ ║
652 095d0ed3 2024-10-05 benni ║ ║ ╚══════════╪════╝ ║ ║
654 095d0ed3 2024-10-05 benni ║ ╚═════════════╪═══════╝ ║
656 095d0ed3 2024-10-05 benni ╚════════════════╪══════════╝
658 095d0ed3 2024-10-05 benni └MOST TRUSTED
661 095d0ed3 2024-10-05 benni 1.3.4 Support for Operating Systems
663 095d0ed3 2024-10-05 benni Most operating systems involve some degree of concurrency, with multiple
664 095d0ed3 2024-10-05 benni tasks vying for system resources. The task management mechanisms described
665 095d0ed3 2024-10-05 benni above provide the 80286 with inherent support for such multi-tasking
666 095d0ed3 2024-10-05 benni systems. Moreover, the advanced memory management features of the 80286
667 095d0ed3 2024-10-05 benni allow the implementation of sophisticated virtual memory systems.
669 095d0ed3 2024-10-05 benni Operating system implementors have found that a multi-level approach to
670 095d0ed3 2024-10-05 benni system services provides better security and more reliable systems. For
671 095d0ed3 2024-10-05 benni example, a very secure kernel might implement critical functions such as
672 095d0ed3 2024-10-05 benni task scheduling and resource allocation, while less fundamental functions
673 095d0ed3 2024-10-05 benni (such asI/O) are built around the kernel. This layered approach also makes
674 095d0ed3 2024-10-05 benni program development and enhancement simpler and facilitates error detection
675 095d0ed3 2024-10-05 benni and debugging. The 80286 supports the layered approach through its
676 095d0ed3 2024-10-05 benni four-level privilege scheme.
679 095d0ed3 2024-10-05 benni 1.4 Organization of This Book
681 095d0ed3 2024-10-05 benni To facilitate the use of this book both as an introduction to the 80286
682 095d0ed3 2024-10-05 benni architecture and as a reference guide, the remaining chapters are divided
683 095d0ed3 2024-10-05 benni into three major parts.
685 095d0ed3 2024-10-05 benni Part I, comprising chapters 2 through 4, should be read by all those who
686 095d0ed3 2024-10-05 benni wish to acquire a basic familiarity with the 80286 architecture. These
687 095d0ed3 2024-10-05 benni chapters provide detailed information on memory segmentation, registers,
688 095d0ed3 2024-10-05 benni addressing modes and the general (application level) 80286 instruction set.
689 095d0ed3 2024-10-05 benni In conjunction with the 80286 Assembly Language Reference Manual, these
690 095d0ed3 2024-10-05 benni chapters provide sufficient information for an assembly language programmer
691 095d0ed3 2024-10-05 benni to design and write application programs.
693 095d0ed3 2024-10-05 benni The chapters in Part I are:
695 095d0ed3 2024-10-05 benni Chapter 2, "Architectural Features." This chapter discusses those features
696 095d0ed3 2024-10-05 benni of the 80286 architecture that are significant for application programmers.
697 095d0ed3 2024-10-05 benni The information presented can also function as an introduction to the
698 095d0ed3 2024-10-05 benni machine for system programmers. Memory organization and segmentation,
699 095d0ed3 2024-10-05 benni processor registers, addressing modes, and instruction formats are all
700 095d0ed3 2024-10-05 benni discussed.
702 095d0ed3 2024-10-05 benni Chapter 3, "Basic Instruction Set." This chapter presents the core
703 095d0ed3 2024-10-05 benni instructions of the 8086 family.
705 095d0ed3 2024-10-05 benni Chapter 4, "Extended Instruction Set." This chapter presents the extended
706 095d0ed3 2024-10-05 benni instructions shared by the 80186 and 80286 processors.
708 095d0ed3 2024-10-05 benni Part II of the book consists of a single chapter:
710 095d0ed3 2024-10-05 benni Chapter 5, "Real Address Mode." This chapter presents the system
711 095d0ed3 2024-10-05 benni programmer's view of the 80286 when the processor is operated in Real
712 095d0ed3 2024-10-05 benni Address Mode.
714 095d0ed3 2024-10-05 benni Part III of the book comprises chapters 6 through 11. Aimed primarily at
715 095d0ed3 2024-10-05 benni system programmers, these chapters discuss the more advanced architectural
716 095d0ed3 2024-10-05 benni features of the 80286, which are available when the processor is in
717 095d0ed3 2024-10-05 benni Protected Mode. Details on memory management, protection mechanisms, and
718 095d0ed3 2024-10-05 benni task switching are provided.
720 095d0ed3 2024-10-05 benni The chapters in Part III are:
722 095d0ed3 2024-10-05 benni Chapter 6, "Virtual Memory." This chapter describes the 80286 address
723 095d0ed3 2024-10-05 benni translation mechanisms that support virtual memory. Segment descriptors,
724 095d0ed3 2024-10-05 benni global and local descriptor tables, and descriptor caches are discussed.
726 095d0ed3 2024-10-05 benni Chapter 7, "Protection." This chapter describes the protection features of
727 095d0ed3 2024-10-05 benni the 80286. Privilege levels, segment attributes, access restrictions, and
728 095d0ed3 2024-10-05 benni call gates are discussed.
730 095d0ed3 2024-10-05 benni Chapter 8, "Tasks and State Transitions." This chapter describes the 80286
731 095d0ed3 2024-10-05 benni mechanisms that support concurrent tasks. Context-switching, task state
732 095d0ed3 2024-10-05 benni segments, task gates, and interrupt tasks are discussed.
734 095d0ed3 2024-10-05 benni Chapter 9, "Interrupts, Traps and Faults." This chapter describes interrupt
735 095d0ed3 2024-10-05 benni and trap handling. Special attention is paid to the exception traps, or
736 095d0ed3 2024-10-05 benni faults, which may occur in Protected Mode. Interrupt gates, trap gates, and
737 095d0ed3 2024-10-05 benni the interrupt descriptor table are discussed.
739 095d0ed3 2024-10-05 benni Chapter 10, "System Control and Initialization." This chapter describes the
740 095d0ed3 2024-10-05 benni actual instructions used to implement the memory management, protection, and
741 095d0ed3 2024-10-05 benni task support features of the 80286. System registers, privileged
742 095d0ed3 2024-10-05 benni instructions, and the initial machine state are discussed.
744 095d0ed3 2024-10-05 benni Chapter 11, "Advanced Topics." This chapter completes Part III with a
745 095d0ed3 2024-10-05 benni description of several advanced topics, including special segment attributes
746 095d0ed3 2024-10-05 benni and pointer validation.
749 095d0ed3 2024-10-05 benni 1.5 Related Publications
751 095d0ed3 2024-10-05 benni The following manuals also contain information of interest to programmers
752 095d0ed3 2024-10-05 benni of 80287 systems:
754 095d0ed3 2024-10-05 benni ■ Introduction to the 80286, order number 210308
755 095d0ed3 2024-10-05 benni ■ ASM286 Assembly Language Reference Manual, order number 121924
756 095d0ed3 2024-10-05 benni ■ 80286 Operating System Writer's Guide, order number 121960
757 095d0ed3 2024-10-05 benni ■ 80286 Hardware Reference Manual, order number 210760
758 095d0ed3 2024-10-05 benni ■ Microprocessor and Peripheral Handbook, order number 230843
759 095d0ed3 2024-10-05 benni ■ PL/M-286 User's Guide, order number 121945
760 095d0ed3 2024-10-05 benni ■ 80287 Support Library Reference Manual, order number 122129
761 095d0ed3 2024-10-05 benni ■ 8086 Software Toolbox Manual, order number 122203 (includes
762 095d0ed3 2024-10-05 benni information about 80287 Emulator Software)
765 095d0ed3 2024-10-05 benni Chapter 2 80286 Base Architecture
767 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
769 095d0ed3 2024-10-05 benni This chapter describes the 80286 application programming environment as
770 095d0ed3 2024-10-05 benni seen by assembly language programmers. It is intended to introduce the
771 095d0ed3 2024-10-05 benni programmer to those features of the 80286 architecture that directly affect
772 095d0ed3 2024-10-05 benni the design and implementation of 80286 application programs.
775 095d0ed3 2024-10-05 benni 2.1 Memory Organization and Segmentation
777 095d0ed3 2024-10-05 benni The main memory of an 80286 system makes up its physical address space.
778 095d0ed3 2024-10-05 benni This address space is organized as a sequence of 8-bit quantities, called
779 095d0ed3 2024-10-05 benni bytes. Each byte is assigned a unique address ranging from 0 up to a maximum
780 095d0ed3 2024-10-05 benni of 2^(20) (1 megabyte) in Real Address Mode, and up to 2^(24) (16 megabytes)
781 095d0ed3 2024-10-05 benni in Protected Mode.
783 095d0ed3 2024-10-05 benni A virtual address space is the organization of memory as viewed by a
784 095d0ed3 2024-10-05 benni program. Virtual address space is also organized in units of bytes. (Other
785 095d0ed3 2024-10-05 benni addressable units such as words, strings, and BCD digits are described below
786 095d0ed3 2024-10-05 benni in section 2.2, "Data Types.") In Real Address Mode, as with the 8086
787 095d0ed3 2024-10-05 benni itself, programs view physical memory directly, inasmuch as they manipulate
788 095d0ed3 2024-10-05 benni pure physical addresses. Thus, the virtual address space is identical to the
789 095d0ed3 2024-10-05 benni physical address space (1 megabyte).
791 095d0ed3 2024-10-05 benni In Protected Mode, however, programs have no direct access to physical
792 095d0ed3 2024-10-05 benni addresses. Instead, memory is viewed as a much larger virtual address space
793 095d0ed3 2024-10-05 benni of 2^(30) bytes (1 gigabyte). This 1 gigabyte virtual address is mapped onto
794 095d0ed3 2024-10-05 benni the Protected Mode's 16-megabyte physical address space by the address
795 095d0ed3 2024-10-05 benni translation mechanisms described in Chapter 6.
797 095d0ed3 2024-10-05 benni The programmer views the virtual address space on the 80286 as a collection
798 095d0ed3 2024-10-05 benni of up to sixteen thousand linear subspaces, each with a specified size or
799 095d0ed3 2024-10-05 benni length. Each of these linear address spaces is called a segment. A segment
800 095d0ed3 2024-10-05 benni is a logical unit of contiguous memory. Segment sizes may range from one
801 095d0ed3 2024-10-05 benni byte up to 64K (65,536) bytes.
803 095d0ed3 2024-10-05 benni 80286 memory segmentation supports the logical structure of programs and
804 095d0ed3 2024-10-05 benni data in memory. Programs are not written as single linear sequences of
805 095d0ed3 2024-10-05 benni instructions and data, but rather as modules of code and data. For example,
806 095d0ed3 2024-10-05 benni program code may include a main routine and several separate procedures.
807 095d0ed3 2024-10-05 benni Data may also be organized into various data structures, some private and
808 095d0ed3 2024-10-05 benni some shared with other programs in the system. Run-time stacks constitute
809 095d0ed3 2024-10-05 benni yet another data requirement. Each of these several modules of code and
810 095d0ed3 2024-10-05 benni data, moreover, may be very different in size or vary dynamically with
811 095d0ed3 2024-10-05 benni program execution.
813 095d0ed3 2024-10-05 benni Segmentation supports this logical structure (see figure 2-1). Each
814 095d0ed3 2024-10-05 benni meaningful module of a program may be separately contained in individual
815 095d0ed3 2024-10-05 benni segments. The degree of modularization, of course, depends on the
816 095d0ed3 2024-10-05 benni requirements of a particular application. Use of segmentation benefits
817 095d0ed3 2024-10-05 benni almost all applications. Programs execute faster and require less space.
818 095d0ed3 2024-10-05 benni Segmentation also simplifies the design of structured software.
821 095d0ed3 2024-10-05 benni 2.2 Data Types
823 095d0ed3 2024-10-05 benni Bytes and words are the fundamental units in which the 80286 manipulates
824 095d0ed3 2024-10-05 benni data, i.e., the fundamental data types.
826 095d0ed3 2024-10-05 benni A byte is 8 contiguous bits starting on an addressable byte boundary. The
827 095d0ed3 2024-10-05 benni bits are numbered 0 through 7, starting from the right. Bit 7 is the most
828 095d0ed3 2024-10-05 benni significant bit:
831 095d0ed3 2024-10-05 benni ┌───┬───┬───┬───┬───┬───┬───┬───┐
833 095d0ed3 2024-10-05 benni └───┴───┴───┴───┴───┴───┴───┴───┘
835 095d0ed3 2024-10-05 benni A word is defined as two contiguous bytes starting on an arbitrary byte
836 095d0ed3 2024-10-05 benni boundary; a word thus contains 16 bits. The bits are numbered 0 through 15,
837 095d0ed3 2024-10-05 benni starting from the right. Bit 15 is the most significant bit. The byte
838 095d0ed3 2024-10-05 benni containing bit 0 of the word is called the low byte; the byte containing
839 095d0ed3 2024-10-05 benni bit 15 is called the high byte.
842 095d0ed3 2024-10-05 benni ┌───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┐
843 095d0ed3 2024-10-05 benni │ HIGH BYTE │ LOW BYTE │
844 095d0ed3 2024-10-05 benni └───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┘
845 095d0ed3 2024-10-05 benni LOCATION N + 1 LOCATION N
847 095d0ed3 2024-10-05 benni Each byte within a word has its own particular address, and the smaller of
848 095d0ed3 2024-10-05 benni the two addresses is used as the address of the word. The byte at this lower
849 095d0ed3 2024-10-05 benni address contains the eight least significant bits of the word, while the
850 095d0ed3 2024-10-05 benni byte at the higher address contains the eight most significant bits. The
851 095d0ed3 2024-10-05 benni arrangement of bytes within words is illustrated in figure 2-2.
853 095d0ed3 2024-10-05 benni Note that a word need not be aligned at an even-numbered byte address. This
854 095d0ed3 2024-10-05 benni allows maximum flexibility in data structures (e.g., records containing
855 095d0ed3 2024-10-05 benni mixed byte and word entries) and efficiency in memory utilization. Although
856 095d0ed3 2024-10-05 benni actual transfers of data between the processor and memory take place at
857 095d0ed3 2024-10-05 benni physically aligned word boundaries, the 80286 converts requests for
858 095d0ed3 2024-10-05 benni unaligned words into the appropriate sequences of requests acceptable to the
859 095d0ed3 2024-10-05 benni memory interface. Such odd aligned word transfers, however, may impact
860 095d0ed3 2024-10-05 benni performance by requiring two memory cycles to transfer the word rather than
861 095d0ed3 2024-10-05 benni one. Data structures (e.g., stacks) should therefore be designed in such a
862 095d0ed3 2024-10-05 benni way that word operands are aligned on word boundaries whenever possible for
863 095d0ed3 2024-10-05 benni maximum system performance. Due to instruction prefetching and queueing
864 095d0ed3 2024-10-05 benni within the CPU, there is no requirement for instructions to be aligned on
865 095d0ed3 2024-10-05 benni word boundaries and no performance loss if they are not.
867 095d0ed3 2024-10-05 benni Although bytes and words are the fundamental data types of operands, the
868 095d0ed3 2024-10-05 benni processor also supports additional interpretations on these bytes or words.
869 095d0ed3 2024-10-05 benni Depending on the instruction referencing the operand, the following
870 095d0ed3 2024-10-05 benni additional data types can be recognized:
873 095d0ed3 2024-10-05 benni A signed binary numeric value contained in an 8-bit byte or a 16-bit word.
874 095d0ed3 2024-10-05 benni All operations assume a 2's complement representation. (Signed 32- and
875 095d0ed3 2024-10-05 benni 64-bit integers are supported using the 80287 Numeric Data Processor.)
878 095d0ed3 2024-10-05 benni An unsigned binary numeric value contained in an 8-bit byte or 16-bit word.
881 095d0ed3 2024-10-05 benni A 32-bit address quantity composed of a segment selector component and an
882 095d0ed3 2024-10-05 benni offset component. Each component is a 16-bit word.
885 095d0ed3 2024-10-05 benni A contiguous sequence of bytes or words. A string may contain from 1 byte
886 095d0ed3 2024-10-05 benni to 64K bytes.
889 095d0ed3 2024-10-05 benni A byte representation of alphanumeric and control characters using the
890 095d0ed3 2024-10-05 benni ASCII standard of character representation.
893 095d0ed3 2024-10-05 benni A byte (unpacked) representation of the decimal digits (0-9).
895 095d0ed3 2024-10-05 benni Packed BCD:
896 095d0ed3 2024-10-05 benni A byte (packed) representation of two decimal digits (0-9). One digit is
897 095d0ed3 2024-10-05 benni stored in each nibble of the byte.
899 095d0ed3 2024-10-05 benni Floating Point:
900 095d0ed3 2024-10-05 benni A signed 32-, 64-, or 80-bit real number representation. (Floating operands
901 095d0ed3 2024-10-05 benni are supported using the 80287 Numeric Processor Configuration.)
903 095d0ed3 2024-10-05 benni Figure 2-3 graphically represents the data types supported by the 80286.
904 095d0ed3 2024-10-05 benni 80286 arithmetic operations may be performed on five types of numbers:
905 095d0ed3 2024-10-05 benni unsigned binary, signed binary (integers), unsigned packed decimal, unsigned
906 095d0ed3 2024-10-05 benni unpacked decimal, and floating point. Binary numbers may be 8 or 16 bits
907 095d0ed3 2024-10-05 benni long. Decimal numbers are stored in bytes; two digits per byte for packed
908 095d0ed3 2024-10-05 benni decimal, one digit per byte for unpacked decimal. The processor always
909 095d0ed3 2024-10-05 benni assumes that the operands specified in arithmetic instructions contain data
910 095d0ed3 2024-10-05 benni that represent valid numbers for the type of instruction being performed.
911 095d0ed3 2024-10-05 benni Invalid data may produce unpredictable results.
913 095d0ed3 2024-10-05 benni Unsigned binary numbers may be either 8 or 16 bits long; all bits are
914 095d0ed3 2024-10-05 benni considered in determining a number's magnitude. The value range of an 8-bit
915 095d0ed3 2024-10-05 benni unsigned binary number is 0-255; 16 bits can represent values from 0 through
916 095d0ed3 2024-10-05 benni 65,535. Addition, subtraction, multiplication and division operations are
917 095d0ed3 2024-10-05 benni available for unsigned binary numbers.
919 095d0ed3 2024-10-05 benni Signed binary numbers (integers) may be either 8 or 16 bits long. The
920 095d0ed3 2024-10-05 benni high-order (leftmost) bit is interpreted as the number's sign: 0 = positive
921 095d0ed3 2024-10-05 benni and 1 = negative. Negative numbers are represented in standard two's
922 095d0ed3 2024-10-05 benni complement notation. Since the high-order bit is used for a sign, the range
923 095d0ed3 2024-10-05 benni of an 8-bit integer is -128 through +127; 16-bit integers may range from
924 095d0ed3 2024-10-05 benni -32,768 through +32,767. The value zero has a positive sign.
926 095d0ed3 2024-10-05 benni Separate multiplication and division operations are provided for both
927 095d0ed3 2024-10-05 benni signed and unsigned binary numbers. The same addition and subtraction
928 095d0ed3 2024-10-05 benni instructions are used with signed or unsigned binary values. Conditional
929 095d0ed3 2024-10-05 benni jump instructions, as well as an "interrupt on overflow" instruction, can
930 095d0ed3 2024-10-05 benni be used following an unsigned operation on an integer to detect overflow
931 095d0ed3 2024-10-05 benni into the sign bit.
933 095d0ed3 2024-10-05 benni Unpacked decimal numbers are stored as unsigned byte quantities. One digit
934 095d0ed3 2024-10-05 benni is stored in each byte. The magnitude of the number is determined from the
935 095d0ed3 2024-10-05 benni low-order half-byte; hexadecimal values 0-9 are valid and are interpreted as
936 095d0ed3 2024-10-05 benni decimal numbers. The high-order half-byte must be zero for multiplication
937 095d0ed3 2024-10-05 benni and division; it may contain any value for addition and subtraction.
939 095d0ed3 2024-10-05 benni Arithmetic on unpacked decimal numbers is performed in two steps. The
940 095d0ed3 2024-10-05 benni unsigned binary addition, subtraction and multiplication operations are used
941 095d0ed3 2024-10-05 benni to produce an intermediate result. An adjustment instruction then changes
942 095d0ed3 2024-10-05 benni the value to a final correct unpacked decimal number. Division is performed
943 095d0ed3 2024-10-05 benni similarly, except that the adjustment is carried out on the two digit
944 095d0ed3 2024-10-05 benni numerator operand in register AX first, followed by an unsigned binary
945 095d0ed3 2024-10-05 benni division instruction that produces a correct result.
947 095d0ed3 2024-10-05 benni Unpacked decimal numbers are similar to the ASCII character representations
948 095d0ed3 2024-10-05 benni of the digits 0-9. Note, however, that the high-order half-byte of an ASCII
949 095d0ed3 2024-10-05 benni numeral is always 3. Unpacked decimal arithmetic may be performed on ASCII
950 095d0ed3 2024-10-05 benni numeric characters under the following conditions:
952 095d0ed3 2024-10-05 benni ■ the high-order half-byte of an ASCII numeral must be set to 0H prior
953 095d0ed3 2024-10-05 benni to multiplication or division.
955 095d0ed3 2024-10-05 benni ■ unpacked decimal arithmetic leaves the high-order half-byte set to 0H;
956 095d0ed3 2024-10-05 benni it must be set to 3 to produce a valid ASCII numeral.
958 095d0ed3 2024-10-05 benni Packed decimal numbers are stored as unsigned byte quantities. The byte is
959 095d0ed3 2024-10-05 benni treated as having one decimal digit in each half-byte (nibble); the digit in
960 095d0ed3 2024-10-05 benni the high-order half-byte is the most significant. Values 0-9 are valid in
961 095d0ed3 2024-10-05 benni each half-byte, and the range of a packed decimal number is 0-99. Additions
962 095d0ed3 2024-10-05 benni and subtractions are performed in two steps. First, an addition or
963 095d0ed3 2024-10-05 benni subtraction instruction is used to produce an intermediate result. Then, an
964 095d0ed3 2024-10-05 benni adjustment operation is performed which changes the intermediate value to a
965 095d0ed3 2024-10-05 benni final correct packed decimal result. Multiplication and division
966 095d0ed3 2024-10-05 benni adjustments are only available for unpacked decimal numbers.
968 095d0ed3 2024-10-05 benni Pointers and addresses are described below in section 2.3.3, "Index,
969 095d0ed3 2024-10-05 benni Pointer, and Base Registers," and in section 3.8, "Address Manipulation
970 095d0ed3 2024-10-05 benni Instructions."
972 095d0ed3 2024-10-05 benni Strings are contiguous bytes or words from 1 to 64K bytes in length. They
973 095d0ed3 2024-10-05 benni generally contain ASCII or other character data representations. The 80286
974 095d0ed3 2024-10-05 benni provides string manipulation instructions to move, examine, or modify a
975 095d0ed3 2024-10-05 benni string (see section 3.7, "Character Translation and String Instructions").
977 095d0ed3 2024-10-05 benni If the 80287 numeric processor extension (NPX) is present in the system ──
978 095d0ed3 2024-10-05 benni see the 80287 NPX book──the 80286 architecture also supports floating point
979 095d0ed3 2024-10-05 benni numbers, 32- and 64-bit integers, and 18-digit BCD data types.
981 095d0ed3 2024-10-05 benni The 80287 Numeric Data Processor supports and stores real numbers in a
982 095d0ed3 2024-10-05 benni three-field binary format as required by IEEE standard 754 for floating
983 095d0ed3 2024-10-05 benni point numerics (see figure 2-3). The number's significant digits are held
984 095d0ed3 2024-10-05 benni in the significand field, the exponent field locates the binary point within
985 095d0ed3 2024-10-05 benni the significant digits (and therefore determines the number's magnitude),
986 095d0ed3 2024-10-05 benni and the sign field indicates whether the number is positive or negative.
987 095d0ed3 2024-10-05 benni (The exponent and significand are analogous to the terms "characteristic"
988 095d0ed3 2024-10-05 benni and "mantissa," typically used to describe floating point numbers on some
989 095d0ed3 2024-10-05 benni computers.) This format is used by the 80287 with various length
990 095d0ed3 2024-10-05 benni significands and exponents to support single precision, double precision and
991 095d0ed3 2024-10-05 benni extended (80-bit) precision floating point data types. Negative numbers
992 095d0ed3 2024-10-05 benni differ from positive numbers only in their sign bits.
995 095d0ed3 2024-10-05 benni Figure 2-1. Segmented Virtual Memory
997 095d0ed3 2024-10-05 benni ┌─ ── ── ── ── ── ── ── ── ┐
998 095d0ed3 2024-10-05 benni 20000╔════════════════╗ 8000╔═══════════════╗
999 095d0ed3 2024-10-05 benni │ ║CS ║ │ ║ ║ 8600╔═══════════════╗
1000 095d0ed3 2024-10-05 benni ║ MAIN ║ ║ PROCEDURE A ║ ║ PROCEDURE ║
1001 095d0ed3 2024-10-05 benni │ ║ PROCEDURE ║ │ ║ ║ ║ B ║
1002 095d0ed3 2024-10-05 benni 0╚════════════════╝ 0╚═══════════════╝ 0╚═══════════════╝
1004 095d0ed3 2024-10-05 benni ╔════════════════╗ 72535╔═══════════════╗ ╔═══════════════╗
1005 095d0ed3 2024-10-05 benni │ ║DS ║ │ ║ ║ ║ ║
1006 095d0ed3 2024-10-05 benni ║ DATA (MAIN) ║ ║ DATA (A) ║ ║ DATA (B) ║
1007 095d0ed3 2024-10-05 benni │ 0╚════════════════╝ │ 0╚═══════════════╝ 0╚═══════════════╝
1008 095d0ed3 2024-10-05 benni 2000╔════════════════╗
1009 095d0ed3 2024-10-05 benni │ ║SS PROCESS ║ │
1010 095d0ed3 2024-10-05 benni ║ STACK ║
1011 095d0ed3 2024-10-05 benni │ 0╚════════════════╝ │
1012 095d0ed3 2024-10-05 benni ╔════════════════╗
1013 095d0ed3 2024-10-05 benni │ ║ES PROCESS-WIDE ║ │
1015 095d0ed3 2024-10-05 benni │ 0╚════════════════╝ │
1016 095d0ed3 2024-10-05 benni └─ ── ── ── ── ── ── ── ── ┘
1017 095d0ed3 2024-10-05 benni CURRENTLY ACCESSIBLE
1020 095d0ed3 2024-10-05 benni Figure 2-2. Bytes and Words in Memory
1024 095d0ed3 2024-10-05 benni All values in hexadecimal. MEMORY VALUES
1026 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1028 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1030 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1031 095d0ed3 2024-10-05 benni C ║ FE ║─┐
1032 095d0ed3 2024-10-05 benni ╠═══════════════════════╣ ├─ WORD AT ADDRESS B CONTAINS FE06
1033 095d0ed3 2024-10-05 benni B ║ 06 ║─┘
1034 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1036 095d0ed3 2024-10-05 benni ╠═══════════════════════╣─┐
1037 095d0ed3 2024-10-05 benni 9 ║ 1F ║ ├─BYTE AT ADDRESS 9 CONTAINS 1F
1038 095d0ed3 2024-10-05 benni ╠═══════════════════════╣─┘
1040 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1041 095d0ed3 2024-10-05 benni 7 ║ 23 ║─┐
1042 095d0ed3 2024-10-05 benni ╠═══════════════════════╣ ├─ WORD AT ADDRESS 6 CONTAINS 23OB
1043 095d0ed3 2024-10-05 benni 6 ║ OB ║─┘
1044 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1046 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1048 095d0ed3 2024-10-05 benni ╠═══════════════════════╣
1049 095d0ed3 2024-10-05 benni 3 ║ 74 ║ ─┐
1050 095d0ed3 2024-10-05 benni ╠═══════════════════════╣─┐├─ WORD AT ADDRESS 2 CONTAINS 74CB
1051 095d0ed3 2024-10-05 benni 2 ║ CB ║ ─┘
1052 095d0ed3 2024-10-05 benni ╠═══════════════════════╣ ├─ WORD AT ADDRESS 1 CONTAINS CB31
1053 095d0ed3 2024-10-05 benni 1 ║ 31 ║ │
1054 095d0ed3 2024-10-05 benni ╠═══════════════════════╣─┘
1056 095d0ed3 2024-10-05 benni ╚═══════════════════════╝
1059 095d0ed3 2024-10-05 benni Figure 2-3. 80286/80287 Supported Data Types
1062 095d0ed3 2024-10-05 benni 7 0 7 0 15 14 8 7 0
1063 095d0ed3 2024-10-05 benni SIGNED ╔╤╤╤╤╤╤╤╗ UNSIGNED ╔╤╤╤╤╤╤╤╗ SIGNED ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1064 095d0ed3 2024-10-05 benni BYTE ║│ │ ║ BYTE ║ │ ║ WORD ║│ │ │ │ ║
1065 095d0ed3 2024-10-05 benni ╚╧══════╝ ╚═══════╝ ╚╧══════╧═══════╝
1066 095d0ed3 2024-10-05 benni SIGN BIT┘└──────┘ │└MSB │ SIGN BIT┘└MSB │
1067 095d0ed3 2024-10-05 benni MAGNITUDE └───────┘ └───────────────┘
1068 095d0ed3 2024-10-05 benni MAGNITUDE MAGNITUDE
1070 095d0ed3 2024-10-05 benni +3 +2 +1 0
1071 095d0ed3 2024-10-05 benni 31 16 15 0
1072 095d0ed3 2024-10-05 benni SIGNED DOUBLE WORD
1073 095d0ed3 2024-10-05 benni Supported by 80287 numeric data processor configuration.
1074 095d0ed3 2024-10-05 benni ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1075 095d0ed3 2024-10-05 benni ║│ │ │ │ │ │ │ │ ║
1076 095d0ed3 2024-10-05 benni ╚╧══════╧═══════╧═══════╧═══════╝
1077 095d0ed3 2024-10-05 benni SIGN BIT┘└MBS │
1078 095d0ed3 2024-10-05 benni └───────────────────────────────┘
1079 095d0ed3 2024-10-05 benni MAGNITUDE
1081 095d0ed3 2024-10-05 benni +7 +6 +5 +4 +3 +2 +1 0
1082 095d0ed3 2024-10-05 benni 63 48 47 32 31 16 15 0
1083 095d0ed3 2024-10-05 benni SIGNED QUAD WORD
1084 095d0ed3 2024-10-05 benni Supported by 80287 numeric data processor configuration.
1085 095d0ed3 2024-10-05 benni ╔╤══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗
1086 095d0ed3 2024-10-05 benni ║│ │ │ │ │ │ │ │ ║
1087 095d0ed3 2024-10-05 benni ╚╧══╧═══╧═══╧═══╧═══╧═══╧═══╧═══╝
1088 095d0ed3 2024-10-05 benni SIGN BIT┘└MSB │
1089 095d0ed3 2024-10-05 benni └──────────────────────────────┘
1090 095d0ed3 2024-10-05 benni MAGNITUDE
1094 095d0ed3 2024-10-05 benni UNSIGNED WORD ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1095 095d0ed3 2024-10-05 benni ║│ │ │ │ ║
1096 095d0ed3 2024-10-05 benni ╚╧══════╧═══════╝
1098 095d0ed3 2024-10-05 benni └───────────────┘
1099 095d0ed3 2024-10-05 benni MAGNITUDE
1102 095d0ed3 2024-10-05 benni 7 0 7 0 7 0
1103 095d0ed3 2024-10-05 benni BINARY CODED DECIMAL ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1104 095d0ed3 2024-10-05 benni (BCD) ║ │ ║ ••• ║ │ │ │ ║
1105 095d0ed3 2024-10-05 benni ╚═══════╝ ╚═══════╧═══════╝
1106 095d0ed3 2024-10-05 benni BCD BCD BCD
1107 095d0ed3 2024-10-05 benni DIGIT N DIGIT 1 DIGIT 0
1110 095d0ed3 2024-10-05 benni 7 0 7 0 7 0
1111 095d0ed3 2024-10-05 benni ASCII ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1112 095d0ed3 2024-10-05 benni ║ │ ║ ••• ║ │ │ │ ║
1113 095d0ed3 2024-10-05 benni ╚═══════╝ ╚═══════╧═══════╝
1114 095d0ed3 2024-10-05 benni ASCII ASCII ASCII
1115 095d0ed3 2024-10-05 benni CHARACTER[N] CHARACTER{1} CHARACTER{0}
1118 095d0ed3 2024-10-05 benni 7 0 7 0 7 0
1119 095d0ed3 2024-10-05 benni PACKED BCD ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1120 095d0ed3 2024-10-05 benni ║ │ ║ ••• ║ │ │ │ ║
1121 095d0ed3 2024-10-05 benni ╚═══════╝ ╚═══════╧═══════╝
1122 095d0ed3 2024-10-05 benni └───┘ └───┘
1123 095d0ed3 2024-10-05 benni MOST LEAST
1124 095d0ed3 2024-10-05 benni SIGNIFICANT SIGNIFICANT
1125 095d0ed3 2024-10-05 benni DIGIT DIGIT
1128 095d0ed3 2024-10-05 benni 7/15 0 7/15 0 7/15 0
1129 095d0ed3 2024-10-05 benni STRING ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1130 095d0ed3 2024-10-05 benni ║ │ ║ ••• ║ │ │ │ ║
1131 095d0ed3 2024-10-05 benni ╚═══════╝ ╚═══════╧═══════╝
1132 095d0ed3 2024-10-05 benni BYTE/WORD N BYTE/WORD BYTE/WORD
1135 095d0ed3 2024-10-05 benni +3 +2 +1 0
1136 095d0ed3 2024-10-05 benni 31 16 15 0
1137 095d0ed3 2024-10-05 benni POINTER ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗
1138 095d0ed3 2024-10-05 benni ║│ │ │ │ │ │ │ │ ║
1139 095d0ed3 2024-10-05 benni ╚╧══════╧═══════╧═══════╧═══════╝
1140 095d0ed3 2024-10-05 benni └───────────────┴───────────────┘
1141 095d0ed3 2024-10-05 benni SELECTOR OFFSET
1143 095d0ed3 2024-10-05 benni +9 +8 +7 +6 +5 +4 +3 +2 +1 0
1145 095d0ed3 2024-10-05 benni FLOATING POINT
1146 095d0ed3 2024-10-05 benni Supported by 80287 numeric data processor configuration.
1147 095d0ed3 2024-10-05 benni ╔╤══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╤═══╗
1148 095d0ed3 2024-10-05 benni ║│ │ │ │ │ │ │ │ │ │ ║
1149 095d0ed3 2024-10-05 benni ╚╧══╧═══╧═══╧═══╧═══╧═══╧═══╧═══╧═══╧═══╝
1150 095d0ed3 2024-10-05 benni SIGN BIT┘└──────────┴───────────────────────────┘
1151 095d0ed3 2024-10-05 benni EXPONENT MAGNITUDE
1154 095d0ed3 2024-10-05 benni 2.3 Registers
1156 095d0ed3 2024-10-05 benni The 80286 contains a total of fourteen registers that are of interest to
1157 095d0ed3 2024-10-05 benni the application programmer. (Five additional registers used by system
1158 095d0ed3 2024-10-05 benni programmers are covered in section 10.1.) As shown in figure 2-4, these
1159 095d0ed3 2024-10-05 benni registers may be grouped into four basic categories:
1161 095d0ed3 2024-10-05 benni ■ General registers. These eight 16-bit general-purpose registers are
1162 095d0ed3 2024-10-05 benni used primarily to contain operands for arithmetic and logical
1163 095d0ed3 2024-10-05 benni operations.
1165 095d0ed3 2024-10-05 benni ■ Segment registers. These four special-purpose registers determine, at
1166 095d0ed3 2024-10-05 benni any given time, which segments of memory are currently addressable.
1168 095d0ed3 2024-10-05 benni ■ Status and Control registers. These three special-purpose registers
1169 095d0ed3 2024-10-05 benni are used to record and alter certain aspects of the 80286 processor
1173 095d0ed3 2024-10-05 benni 2.3.1 General Registers
1175 095d0ed3 2024-10-05 benni The general registers of the 80286 are the 16-bit registers AX, BX, CX, DX,
1176 095d0ed3 2024-10-05 benni SP, BP, SI, and DI. These registers are used interchangeably to contain the
1177 095d0ed3 2024-10-05 benni operands of logical and arithmetic operations.
1179 095d0ed3 2024-10-05 benni Some instructions and addressing modes (see section 2.4), however, dedicate
1180 095d0ed3 2024-10-05 benni certain general registers to specific uses. BX and BP are often used to
1181 095d0ed3 2024-10-05 benni contain the base address of data structures in memory (for example, the
1182 095d0ed3 2024-10-05 benni starting address of an array); for this reason, they are often referred to
1183 095d0ed3 2024-10-05 benni as the base registers. Similarly, SI and DI are often used to contain an
1184 095d0ed3 2024-10-05 benni index value that will be incremented to step through a data structure; these
1185 095d0ed3 2024-10-05 benni two registers are called the index registers. Finally, SP and BP are used
1186 095d0ed3 2024-10-05 benni for stack manipulation. Both SP and BP normally contain offsets into the
1187 095d0ed3 2024-10-05 benni current stack. SP generally contains the offset of the top of the stack and
1188 095d0ed3 2024-10-05 benni BP contains the offset or base address of the current stack frame. The use
1189 095d0ed3 2024-10-05 benni of these general-purpose registers for operand addressing is discussed in
1190 095d0ed3 2024-10-05 benni section 2.3.3, "Index, Pointer, and Base Registers." Register usage for
1191 095d0ed3 2024-10-05 benni individual instructions is discussed in chapters 3 and 4.
1193 095d0ed3 2024-10-05 benni As shown in figure 2-4, eight byte registers overlap four of the 16-bit
1194 095d0ed3 2024-10-05 benni general registers. These registers are named AH, BH, CH, and DH (high
1195 095d0ed3 2024-10-05 benni bytes); and AL, BL, CL, and DL (low bytes); they overlap AX, BX, CX, and DX.
1196 095d0ed3 2024-10-05 benni These registers can be used either in their entirety or as individual 8-bit
1197 095d0ed3 2024-10-05 benni registers. This dual interpretation simplifies the handling of both 8- and
1198 095d0ed3 2024-10-05 benni 16-bit data elements.
1201 095d0ed3 2024-10-05 benni Figure 2-4. 80286 Base Architecture Register Set
1203 095d0ed3 2024-10-05 benni 16-BIT SPECIAL
1204 095d0ed3 2024-10-05 benni REGISTER REGISTER
1205 095d0ed3 2024-10-05 benni NAME FUNCTIONS
1206 095d0ed3 2024-10-05 benni GENERAL REGISTERS 7 0 7 0
1207 095d0ed3 2024-10-05 benni ┌─ ╔══════╤══════╗─┐
1208 095d0ed3 2024-10-05 benni │ AX ║ AH │ AL ║ │
1209 095d0ed3 2024-10-05 benni BYTE │ ╟──────┼──────╢ ├─MULTIPLY/DIVIDE
1210 095d0ed3 2024-10-05 benni ADDRESSABLE │ DX ║ DH │ DL ║ │ I/O INSTRUCTIONS
1211 095d0ed3 2024-10-05 benni (8-BIT─┤ ╟──────┼──────╢═╡
1212 095d0ed3 2024-10-05 benni REGISTER │ CX ║ CH │ CL ║ ├─LOOP/SHIFT/REPEAT COUNT
1213 095d0ed3 2024-10-05 benni NAMES │ ╟──────┼──────╢═╡
1214 095d0ed3 2024-10-05 benni SHOWN) │ BX ║ BH │ BL ║ │
1215 095d0ed3 2024-10-05 benni └─ ╟──────┴──────╢ ├─BASE REGISTERS
1217 095d0ed3 2024-10-05 benni ╟─────────────╢═╡
1219 095d0ed3 2024-10-05 benni ╟─────────────╢ ├─INDEX REGISTERS
1221 095d0ed3 2024-10-05 benni ╟─────────────╢═╡
1222 095d0ed3 2024-10-05 benni SP ║ ║ ├─STACK POINTER
1223 095d0ed3 2024-10-05 benni ╚═════════════╝─┘
1226 095d0ed3 2024-10-05 benni SEGMENT REGISTERS 15 0
1227 095d0ed3 2024-10-05 benni ╔═════════════╗
1228 095d0ed3 2024-10-05 benni CS ║ ║ CODE SEGMENT SELECTOR
1229 095d0ed3 2024-10-05 benni ╟─────────────╢
1230 095d0ed3 2024-10-05 benni DS ║ ║ DATA SEGMENT SELECTOR
1231 095d0ed3 2024-10-05 benni ╟─────────────╢
1232 095d0ed3 2024-10-05 benni SS ║ ║ STACK SEGMENT SELECTOR
1233 095d0ed3 2024-10-05 benni ╟─────────────╢
1234 095d0ed3 2024-10-05 benni ES ║ ║ EXTRA SEGMENT SELECTOR
1235 095d0ed3 2024-10-05 benni ╚═════════════╝
1237 095d0ed3 2024-10-05 benni STATUS AND CONTROL 15 0
1238 095d0ed3 2024-10-05 benni REGISTERS ╔═════════════╗
1239 095d0ed3 2024-10-05 benni F ║ ║ FLAGS
1240 095d0ed3 2024-10-05 benni ╟─────────────╢
1241 095d0ed3 2024-10-05 benni IP ║ ║ INSTRUCTION POINTER
1242 095d0ed3 2024-10-05 benni ╟─────────────╢
1243 095d0ed3 2024-10-05 benni MSW ║ ║ MACHINE STATUS WORD
1244 095d0ed3 2024-10-05 benni ╚═════════════╝
1247 095d0ed3 2024-10-05 benni 2.3.2 Memory Segmentation and Segment Registers
1249 095d0ed3 2024-10-05 benni Complete programs generally consist of many different code modules (or
1250 095d0ed3 2024-10-05 benni segments), and different types of data segments. However, at any given time
1251 095d0ed3 2024-10-05 benni during program execution, only a small subset of a program's segments are
1252 095d0ed3 2024-10-05 benni actually in use. Generally, this subset will include code, data, and
1253 095d0ed3 2024-10-05 benni possibly a stack. The 80286 architecture takes advantage of this by
1254 095d0ed3 2024-10-05 benni providing mechanisms to support direct access to the working set of a
1255 095d0ed3 2024-10-05 benni program's execution environment and access to additional segments on
1258 095d0ed3 2024-10-05 benni At any given instant, four segments of memory are immediately accessible to
1259 095d0ed3 2024-10-05 benni an executing 80286 program. The segment registers DS, ES, SS, and CS are
1260 095d0ed3 2024-10-05 benni used to identify these four current segments. Each of these registers
1261 095d0ed3 2024-10-05 benni specifies a particular kind of segment, as characterized by the associated
1262 095d0ed3 2024-10-05 benni mnemonics ("code," "stack," "data," or "extra") shown in figure 2-4.
1264 095d0ed3 2024-10-05 benni An executing program is provided with concurrent access to the four
1265 095d0ed3 2024-10-05 benni individual segments of memory──a code segment, a stack segment, and two
1266 095d0ed3 2024-10-05 benni data segments──by means of the four segment registers. Each may be said to
1267 095d0ed3 2024-10-05 benni select a segment, since it uniquely determines the one particular segment
1268 095d0ed3 2024-10-05 benni from among the numerous segments in memory, which is to be immediately
1269 095d0ed3 2024-10-05 benni accessible at highest speed. Thus, the 16-bit contents of a segment register
1270 095d0ed3 2024-10-05 benni is called a segment selector.
1272 095d0ed3 2024-10-05 benni Once a segment is selected, a base address is associated with it. To
1273 095d0ed3 2024-10-05 benni address an element within a segment, a 16-bit offset from the segment's base
1274 095d0ed3 2024-10-05 benni address must be supplied. The 16-bit segment selector and the 16-bit offset
1275 095d0ed3 2024-10-05 benni taken together form the high and low order halves, respectively, of a
1276 095d0ed3 2024-10-05 benni 32-bit virtual address pointer. Once a segment is selected, only the lower
1277 095d0ed3 2024-10-05 benni 16-bits of the pointer, called the offset, generally need to be specified by
1278 095d0ed3 2024-10-05 benni an instruction. Simple rules define which segment register is used to form
1279 095d0ed3 2024-10-05 benni an address when only a 16-bit offset is specified.
1281 095d0ed3 2024-10-05 benni An executing program requires, first of all, that its instructions reside
1282 095d0ed3 2024-10-05 benni somewhere in memory. The segment of memory containing the currently
1283 095d0ed3 2024-10-05 benni executing sequence of instructions is known as the current code segment; it
1284 095d0ed3 2024-10-05 benni is specified by means of the CS register. All instructions are fetched from
1285 095d0ed3 2024-10-05 benni this code segment, using as an offset the contents of the instruction
1286 095d0ed3 2024-10-05 benni pointer (IP). The CS:IP register combination therefore forms the full 32-bit
1287 095d0ed3 2024-10-05 benni pointer for the next sequential program instruction. The CS register is
1288 095d0ed3 2024-10-05 benni manipulated indirectly. Transitions from one code segment to another (e.g.,
1289 095d0ed3 2024-10-05 benni a procedure call) are effected implicitly as the result of control-transfer
1290 095d0ed3 2024-10-05 benni instructions, interrupts, and trap operations.
1292 095d0ed3 2024-10-05 benni Stacks play a fundamental role in the 80286 architecture; subroutine calls,
1293 095d0ed3 2024-10-05 benni for example, involve a number of implicit stack operations. Thus, an
1294 095d0ed3 2024-10-05 benni executing program will generally require a region of memory for its stack.
1295 095d0ed3 2024-10-05 benni The segment containing this region is known as the current stack segment,
1296 095d0ed3 2024-10-05 benni and it is specified by means of the SS register. All stack operations are
1297 095d0ed3 2024-10-05 benni performed within this segment, usually in terms of address offsets contained
1298 095d0ed3 2024-10-05 benni in the stack pointer (SP) and stack frame base (BP) registers. Unlike CS,
1299 095d0ed3 2024-10-05 benni the SS register can be loaded explicitly for dynamic stack definition.
1301 095d0ed3 2024-10-05 benni Beyond their code and stack requirements, most programs must also fetch and
1302 095d0ed3 2024-10-05 benni store data in memory. The DS and ES registers allow the specification of two
1303 095d0ed3 2024-10-05 benni data segments, each addressable by the currently executing program.
1304 095d0ed3 2024-10-05 benni Accessibility to two separate data areas supports differentiation and
1305 095d0ed3 2024-10-05 benni access requirements like local procedure data and global process data. An
1306 095d0ed3 2024-10-05 benni operand within a data segment is addressed by specifying its offset either
1307 095d0ed3 2024-10-05 benni directly in an instruction or indirectly via index and/or base registers
1308 095d0ed3 2024-10-05 benni (described in the next subsection).
1310 095d0ed3 2024-10-05 benni Depending on the data structure (e.g., the way data is parceled into one or
1311 095d0ed3 2024-10-05 benni more segments), a program may require access to multiple data segments. To
1312 095d0ed3 2024-10-05 benni access additional segments, the DS and ES registers can be loaded under
1313 095d0ed3 2024-10-05 benni program control during the course of a program's execution. This simply
1314 095d0ed3 2024-10-05 benni requires loading the appropriate data pointer prior to accessing the data.
1316 095d0ed3 2024-10-05 benni The interpretation of segment selector values depends on the operating mode
1317 095d0ed3 2024-10-05 benni of the processor. In Real Address Mode, a segment selector is a physical
1318 095d0ed3 2024-10-05 benni address (figure 2-5). In Protected Mode, a segment selector selects a
1319 095d0ed3 2024-10-05 benni segment of the user's virtual address space (figure 2-6). An intervening
1320 095d0ed3 2024-10-05 benni level of logical-to-physical address translation converts the logical
1321 095d0ed3 2024-10-05 benni address to a physical memory address. Chapter 6, "Memory Management,"
1322 095d0ed3 2024-10-05 benni provides a detailed discussion of Protected Mode addressing. In general,
1323 095d0ed3 2024-10-05 benni considerations of selector formats and the details of memory mapping need
1324 095d0ed3 2024-10-05 benni not concern the application programmer.
1327 095d0ed3 2024-10-05 benni 2.3.3 Index, Pointer, and Base Registers
1329 095d0ed3 2024-10-05 benni Five of the general-purpose registers are available for offset address
1330 095d0ed3 2024-10-05 benni calculations. These five registers, shown in figure 2-4, are SP, BP, BX,
1331 095d0ed3 2024-10-05 benni SI, and DI. SP is called a pointer register; BP and BX are called base
1332 095d0ed3 2024-10-05 benni registers; SI and DI are called index registers.
1334 095d0ed3 2024-10-05 benni As described in the previous section, segment registers define the set of
1335 095d0ed3 2024-10-05 benni four segments currently addressable by a program. A pointer, base, or index
1336 095d0ed3 2024-10-05 benni register may contain an offset value relative to the start of one of these
1337 095d0ed3 2024-10-05 benni segments; it thereby points to a particular operand's location within that
1338 095d0ed3 2024-10-05 benni segment. To allow for efficient computations of effective address offsets,
1339 095d0ed3 2024-10-05 benni all base and index registers may participate interchangeably as operands in
1340 095d0ed3 2024-10-05 benni most arithmetical operations.
1342 095d0ed3 2024-10-05 benni Stack operations are facilitated by the stack pointer (SP) and stack frame
1343 095d0ed3 2024-10-05 benni base (BP) registers. By specifying offsets into the current stack segment,
1344 095d0ed3 2024-10-05 benni each of these registers provides access to data on the stack. The SP
1345 095d0ed3 2024-10-05 benni register is the customary top-of-stack pointer, addressing the uppermost
1346 095d0ed3 2024-10-05 benni datum on a push-down stack. It is referenced implicitly by PUSH and POP
1347 095d0ed3 2024-10-05 benni operations, subroutine calls, and interrupt operations. The BP register
1348 095d0ed3 2024-10-05 benni provides yet another offset into the stack segment. The existence of this
1349 095d0ed3 2024-10-05 benni stack relative base register, in conjunction with certain addressing modes
1350 095d0ed3 2024-10-05 benni described in section 2.4.3, is particularly useful for accessing data
1351 095d0ed3 2024-10-05 benni structures, variables and dynamically allocated work space within the stack.
1353 095d0ed3 2024-10-05 benni Stacks in the 80286 are implemented in memory and are located by the stack
1354 095d0ed3 2024-10-05 benni segment register (SS) and the stack pointer register (SP). A system may have
1355 095d0ed3 2024-10-05 benni an unlimited number of stacks, and a stack may be up to 64K bytes long, the
1356 095d0ed3 2024-10-05 benni maximum length of a segment.
1358 095d0ed3 2024-10-05 benni One stack is directly addressable at a time; this is the current stack,
1359 095d0ed3 2024-10-05 benni often referred to simply as "the" stack. SP contains the current top of the
1360 095d0ed3 2024-10-05 benni stack (TOS). In other words, SP contains the offset to the top of the push
1361 095d0ed3 2024-10-05 benni down stack from the stack segment's base address. Note, however, that the
1362 095d0ed3 2024-10-05 benni stack's base address (contained in SS) is not the "bottom" of the stack
1363 095d0ed3 2024-10-05 benni (figure 2-7).
1365 095d0ed3 2024-10-05 benni 80286 stack entries are 16 bits wide. Instructions operate on the stack by
1366 095d0ed3 2024-10-05 benni adding and removing stack items one word at a time. An item is pushed onto
1367 095d0ed3 2024-10-05 benni the stack (see figure 2-8) by decrementing SP by 2 and writing the item at
1368 095d0ed3 2024-10-05 benni the new TOS. An item is popped off the stack by copying it from TOS and then
1369 095d0ed3 2024-10-05 benni incrementing SP by 2. In other words, the stack grows down in memory toward
1370 095d0ed3 2024-10-05 benni its base address. Stack operations never move items on the stack; nor do
1371 095d0ed3 2024-10-05 benni they erase them. The top of the stack changes only as a result of updating
1372 095d0ed3 2024-10-05 benni the stack pointer.
1374 095d0ed3 2024-10-05 benni The stack frame base pointer (BP) is often used to access elements on the
1375 095d0ed3 2024-10-05 benni stack relative to a fixed point on the stack rather than relative to the
1376 095d0ed3 2024-10-05 benni current TOS. It typically identifies the base address of the current
1377 095d0ed3 2024-10-05 benni stack frame established for the current procedure (figure 2-9). If an index
1378 095d0ed3 2024-10-05 benni register is used relative to BP (e.g., base + index addressing mode using BP
1379 095d0ed3 2024-10-05 benni as the base), the offset will be calculated automatically in the current
1380 095d0ed3 2024-10-05 benni stack segment.
1382 095d0ed3 2024-10-05 benni Accessing data structures in data segments is facilitated by the BX
1383 095d0ed3 2024-10-05 benni register, which has the same function in addressing operands within data
1384 095d0ed3 2024-10-05 benni segments that BP does for stack segments. They are called base registers
1385 095d0ed3 2024-10-05 benni because they may contain an offset to the base of a data structure. The
1386 095d0ed3 2024-10-05 benni similar usage of these two registers is especially important when discussing
1387 095d0ed3 2024-10-05 benni addressing modes (see section 2.4, "Addressing Modes").
1389 095d0ed3 2024-10-05 benni Operations on data are also facilitated by the SI and DI registers. By
1390 095d0ed3 2024-10-05 benni specifying an offset relative to the start of the currently addressable data
1391 095d0ed3 2024-10-05 benni segment, an index register can be used to address an operand in the segment.
1392 095d0ed3 2024-10-05 benni If an index register is used in conjunction with the BX base register
1393 095d0ed3 2024-10-05 benni (i.e., base + index addressing) to form an offset address, the data is also
1394 095d0ed3 2024-10-05 benni assumed to reside in the current data segment. As a rule, data referenced
1395 095d0ed3 2024-10-05 benni through an index register or BX is presumed to reside in the current data
1396 095d0ed3 2024-10-05 benni segment. That is, if an instruction invokes addressing for one of its
1397 095d0ed3 2024-10-05 benni operands using either BX, DI, SI, or BX with SI or DI, the contents of the
1398 095d0ed3 2024-10-05 benni register(s) (BX, DI, or SI) implicitly specify an offset in the current data
1399 095d0ed3 2024-10-05 benni segment. As previously mentioned, data referenced via SP, BP or BP with SI
1400 095d0ed3 2024-10-05 benni or DI implicitly specify an operand in the current stack segment (refer to
1401 095d0ed3 2024-10-05 benni table 2-1).
1403 095d0ed3 2024-10-05 benni There are two exceptions to the rules listed above. The first concerns the
1404 095d0ed3 2024-10-05 benni operation of certain 80286 string instructions. For the most flexibility,
1405 095d0ed3 2024-10-05 benni these instructions assume that the DI register addresses destination strings
1406 095d0ed3 2024-10-05 benni not in the data segment, but rather in the extra segment (ES register).
1407 095d0ed3 2024-10-05 benni This allows movement of strings between different segments. This has led to
1408 095d0ed3 2024-10-05 benni the descriptive names "source index" and "destination index." In all cases
1409 095d0ed3 2024-10-05 benni other than string instructions, however, the SI and DI registers may be used
1410 095d0ed3 2024-10-05 benni interchangeably to reference either source or destination operands.
1412 095d0ed3 2024-10-05 benni A second more general override capability allows the programmer complete
1413 095d0ed3 2024-10-05 benni control of which segment is used for a specific operation. Segment-override
1414 095d0ed3 2024-10-05 benni prefixes, discussed in section 2.4.3, allow the index and base registers to
1415 095d0ed3 2024-10-05 benni address data in any of the four currently addressable segments.
1418 095d0ed3 2024-10-05 benni Table 2-1. Implied Segment Usage by Index, Pointer, and Base Registers
1420 095d0ed3 2024-10-05 benni Register Implied Segment
1424 095d0ed3 2024-10-05 benni DI DS, ES for String Operations
1425 095d0ed3 2024-10-05 benni BP + SI, DI SS
1426 095d0ed3 2024-10-05 benni BX + SI, DI DS
1428 095d0ed3 2024-10-05 benni ────────────────────────────────────────────────────────────────────────────
1430 095d0ed3 2024-10-05 benni All implied Segment usage, except SP to SS and DI to ES for String
1431 095d0ed3 2024-10-05 benni Operations, may be explicitly specified with a segment override prefix for
1432 095d0ed3 2024-10-05 benni any of the four segments. The prefix precedes the instruction for which
1433 095d0ed3 2024-10-05 benni explicit reference is desired.
1434 095d0ed3 2024-10-05 benni ────────────────────────────────────────────────────────────────────────────
1437 095d0ed3 2024-10-05 benni Figure 2-5. Real Address Mode Segment Selector Interpretation
1439 095d0ed3 2024-10-05 benni ╔═══════════════╗─┐
1442 095d0ed3 2024-10-05 benni ┌─╠═══════════════╣ │ 1 MEGABYTE
1443 095d0ed3 2024-10-05 benni SEGMENT 64K BYTES ─┤ ║ SEG 1 ║ ├─ PHYSICAL
1444 095d0ed3 2024-10-05 benni ┌──────────────────────►└─╠═══════════════╣ │ ADDRESS
1445 095d0ed3 2024-10-05 benni │ BASE ADDRESS ║ ║ │ SPACE
1447 095d0ed3 2024-10-05 benni ╔═════╧══════╤══════╗ ║ ║ │
1448 095d0ed3 2024-10-05 benni ║ SELECTOR │ 0000 ║ ╚═══════════════╝─┘
1449 095d0ed3 2024-10-05 benni ╚════════════╧══════╝
1451 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
1453 095d0ed3 2024-10-05 benni 1. The selector inentifies a segment in physical memory.
1454 095d0ed3 2024-10-05 benni 2. A selector specifies the segments base address, Modulo 16, within
1455 095d0ed3 2024-10-05 benni the 1 Megabyte address space.
1456 095d0ed3 2024-10-05 benni 3. The selector is the 16 most significant bits of a segments physical
1457 095d0ed3 2024-10-05 benni base address.
1458 095d0ed3 2024-10-05 benni 4. The values of selectors determines the amount they overlap in real
1460 095d0ed3 2024-10-05 benni 5. Segments may overlap by increments of 16 bytes. Overlap ranges from
1461 095d0ed3 2024-10-05 benni complete (SEG 1 = SEG 1) to none (SEG 1 ╪ SEG 2 ± 64K).
1462 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
1465 095d0ed3 2024-10-05 benni Figure 2-6. Protected Mode Segment Selector Interpretation
1467 095d0ed3 2024-10-05 benni ╔════════════╗─┐
1468 095d0ed3 2024-10-05 benni ║ SEG 3FFF ║ │
1469 095d0ed3 2024-10-05 benni ╠════════════╣ │
1470 095d0ed3 2024-10-05 benni ║ SEG 3FFE ║ │
1471 095d0ed3 2024-10-05 benni ┌───────────────────────────►╠════════════╣ │
1472 095d0ed3 2024-10-05 benni ╔═══════╧══════╗ ║ SEG 3FFD ║ │
1473 095d0ed3 2024-10-05 benni ║ SELECTOR ║ ┌─╠════════════╣ │
1474 095d0ed3 2024-10-05 benni ╚══════════════╝ 1 TO 64K BYTES─┤ ║ SEG 3FFC ║ │
1475 095d0ed3 2024-10-05 benni └─╠════════════╣ │
1476 095d0ed3 2024-10-05 benni ║ SEG 3FFB ║ │
1477 095d0ed3 2024-10-05 benni ╠════════════╣ │ 1 GIGABYTE
1478 095d0ed3 2024-10-05 benni ≈ ≈ ├─ VIRTUAL
1479 095d0ed3 2024-10-05 benni ╠════════════╣ │ ADDRESS
1480 095d0ed3 2024-10-05 benni ║ SEG 4 ║ │ SPACE
1481 095d0ed3 2024-10-05 benni ╠════════════╣ │
1482 095d0ed3 2024-10-05 benni ║ SEG 3 ║ │
1483 095d0ed3 2024-10-05 benni ╠════════════╣ │
1484 095d0ed3 2024-10-05 benni ║ SEG 2 ║ │
1485 095d0ed3 2024-10-05 benni ╠════════════╣ │
1486 095d0ed3 2024-10-05 benni ║ SEG 1 ║ │
1487 095d0ed3 2024-10-05 benni ╠════════════╣ │
1488 095d0ed3 2024-10-05 benni ║ SEG 0 ║ │
1489 095d0ed3 2024-10-05 benni ╚════════════╝─┘
1491 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
1493 095d0ed3 2024-10-05 benni 1. A selector uniquely identifies (names) one of 16K possible segments
1494 095d0ed3 2024-10-05 benni in the task's virtual address space.
1495 095d0ed3 2024-10-05 benni 2. The selector value does not specify the segment's location in
1496 095d0ed3 2024-10-05 benni physical memory.
1497 095d0ed3 2024-10-05 benni 3. The selector does not imply any overlap with other segments (This
1498 095d0ed3 2024-10-05 benni depends on the base address of the segment via the memory management
1499 095d0ed3 2024-10-05 benni and protection information).
1500 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
1503 095d0ed3 2024-10-05 benni Figure 2-7. 80286 Stack
1505 095d0ed3 2024-10-05 benni ╔═════════════════╗ LOGICAL
1506 095d0ed3 2024-10-05 benni ║ ║◄─── BOTTOM OF STACK
1507 095d0ed3 2024-10-05 benni ╠═════════════════╣ (initial SP value)
1509 095d0ed3 2024-10-05 benni ╠═════════════════╣
1511 095d0ed3 2024-10-05 benni ╠═════════════════╣
1512 095d0ed3 2024-10-05 benni ║ ║ ▲ POP-UP
1513 095d0ed3 2024-10-05 benni ╠═════════════════╣ │
1514 095d0ed3 2024-10-05 benni ┌───────────►║ ║◄─── LOGICAL TOP OF STACK
1515 095d0ed3 2024-10-05 benni │ ╠═════════════════╣ │
1516 095d0ed3 2024-10-05 benni │ ║ ║ ▼ PUSH-DOWN
1517 095d0ed3 2024-10-05 benni ╔══════╤═══╧══╗ ║ ║
1518 095d0ed3 2024-10-05 benni ║ SS │ SP ║ ║ ║
1519 095d0ed3 2024-10-05 benni ╚══╤═══╧══════╝ ║ ║
1523 095d0ed3 2024-10-05 benni └───────────────────►╚═════════════════╝ STACK SEGMENT BASE ADDRESS
1526 095d0ed3 2024-10-05 benni Figure 2-8. Stack Operation
1528 095d0ed3 2024-10-05 benni STACK OPERATION FOR CODE SEQUENCE:
1529 095d0ed3 2024-10-05 benni PUSH AX STACK
1530 095d0ed3 2024-10-05 benni POP AX SEGMENT
1531 095d0ed3 2024-10-05 benni POP BX ┌──────────────┐ • • ▲
1532 095d0ed3 2024-10-05 benni │EXISTING STACK│ ╟─────────╢ │ BOTTOM
1533 095d0ed3 2024-10-05 benni │ BEFORE PUSH │ 1062 ║ 0 0 0 0 ║ │ OF
1534 095d0ed3 2024-10-05 benni └──────────────┘ ╟─────────╢ │ STACK
1535 095d0ed3 2024-10-05 benni 1060 ║ 1 1 1 1 ║
1536 095d0ed3 2024-10-05 benni ╟─────────╢
1537 095d0ed3 2024-10-05 benni 105E ║ 2 2 2 2 ║
1538 095d0ed3 2024-10-05 benni ╟─────────╢
1539 095d0ed3 2024-10-05 benni 105C ║ 3 3 3 3 ║
1540 095d0ed3 2024-10-05 benni ╟─────────╢
1541 095d0ed3 2024-10-05 benni 105A ║ 4 4 4 4 ║
1542 095d0ed3 2024-10-05 benni ╟─────────╢
1543 095d0ed3 2024-10-05 benni ┌──────────────► 1058 ║ 5 5 5 5 ║
1544 095d0ed3 2024-10-05 benni SS │ SP ╟─────────╢─┐
1545 095d0ed3 2024-10-05 benni ╔══════════╤═════╧════╗ 1056 ║ 6 6 6 6 ║ │
1546 095d0ed3 2024-10-05 benni ║ SELECTOR │ OFFSET ║ ╟─────────╢ │ NOT
1547 095d0ed3 2024-10-05 benni ╚════╤═════╧══════════╝ 1054 ║ 7 7 7 7 ║ ├─ PRESENTLY
1548 095d0ed3 2024-10-05 benni │ ╟─────────╢ │ USED
1549 095d0ed3 2024-10-05 benni │ 1052 ║ 8 8 8 8 ║ │
1550 095d0ed3 2024-10-05 benni │ ╟─────────╢─┘
1551 095d0ed3 2024-10-05 benni │ 1050 ║ 9 9 9 9 ║
1553 095d0ed3 2024-10-05 benni └──────────────────────────► 0000 ╟─────────╢
1559 095d0ed3 2024-10-05 benni ╟─────────╢
1560 095d0ed3 2024-10-05 benni 1062 ║ 0 0 0 0 ║
1561 095d0ed3 2024-10-05 benni ╟─────────╢
1562 095d0ed3 2024-10-05 benni 1060 ║ 1 1 1 1 ║
1563 095d0ed3 2024-10-05 benni ╟─────────╢
1564 095d0ed3 2024-10-05 benni 105E ║ 2 2 2 2 ║
1565 095d0ed3 2024-10-05 benni ╟─────────╢
1566 095d0ed3 2024-10-05 benni 105C ║ 3 3 3 3 ║
1567 095d0ed3 2024-10-05 benni ╟─────────╢
1568 095d0ed3 2024-10-05 benni 105A ║ 4 4 4 4 ║ PUSH AX
1569 095d0ed3 2024-10-05 benni ╟─────────╢╔═════════╗
1570 095d0ed3 2024-10-05 benni ┌──────────────► 1058 ║ 5 5 5 5 ║║ A A A A ║
1571 095d0ed3 2024-10-05 benni SS │ SP ╟─────────╢╚══╤══════╝
1572 095d0ed3 2024-10-05 benni ╔══════════╤═════╧════╗ 1056 ║ A A A A ║◄──┘
1573 095d0ed3 2024-10-05 benni ║ SELECTOR │ OFFSET ║ ╟─────────╢
1574 095d0ed3 2024-10-05 benni ╚════╤═════╧══════════╝ 1054 ║ 7 7 7 7 ║
1575 095d0ed3 2024-10-05 benni │ ╟─────────╢
1576 095d0ed3 2024-10-05 benni │ 1052 ║ 8 8 8 8 ║
1577 095d0ed3 2024-10-05 benni │ ╟─────────╢
1578 095d0ed3 2024-10-05 benni │ 1050 ║ 9 9 9 9 ║
1580 095d0ed3 2024-10-05 benni └──────────────────────────► 0000 ╟─────────╢
1586 095d0ed3 2024-10-05 benni ╟─────────╢
1587 095d0ed3 2024-10-05 benni 1062 ║ 0 0 0 0 ║
1588 095d0ed3 2024-10-05 benni ╟─────────╢
1589 095d0ed3 2024-10-05 benni 1060 ║ 1 1 1 1 ║
1590 095d0ed3 2024-10-05 benni ╟─────────╢
1591 095d0ed3 2024-10-05 benni 105E ║ 2 2 2 2 ║
1592 095d0ed3 2024-10-05 benni ╟─────────╢ POP BX
1593 095d0ed3 2024-10-05 benni 105C ║ 3 3 3 3 ║ ╔═════════╗
1594 095d0ed3 2024-10-05 benni ╟─────────╢ ║ 5 5 5 5 ║
1595 095d0ed3 2024-10-05 benni 105A ║ 4 4 4 4 ║ ╚═════════╝
1596 095d0ed3 2024-10-05 benni ╟─────────╢ ▲
1597 095d0ed3 2024-10-05 benni ┌──────────────► 1058 ║ 5 5 5 5 ║──────┘
1598 095d0ed3 2024-10-05 benni SS │ SP ╟─────────╢
1599 095d0ed3 2024-10-05 benni ╔══════════╤═════╧════╗ 1056 ║ A A A A ║──────┐
1600 095d0ed3 2024-10-05 benni ║ SELECTOR │ OFFSET ║ ╟─────────╢ ▼
1601 095d0ed3 2024-10-05 benni ╚════╤═════╧══════════╝ 1054 ║ 7 7 7 7 ║ ╔═════════╗
1602 095d0ed3 2024-10-05 benni │ ╟─────────╢ ║ A A A A ║
1603 095d0ed3 2024-10-05 benni │ 1052 ║ 8 8 8 8 ║ ╚═════════╝
1604 095d0ed3 2024-10-05 benni │ ╟─────────╢ POP AX
1605 095d0ed3 2024-10-05 benni │ 1050 ║ 9 9 9 9 ║
1607 095d0ed3 2024-10-05 benni └──────────────────────────► 0000 ╟─────────╢
1611 095d0ed3 2024-10-05 benni Figure 2-9. BP Usage as a Stack Frame Base Pointer
1613 095d0ed3 2024-10-05 benni BP is a constant pointer to stack based variables and work space. All
1614 095d0ed3 2024-10-05 benni references use BP and are independent of SP, which may vary during a routine
1615 095d0ed3 2024-10-05 benni execution.
1619 095d0ed3 2024-10-05 benni PUSH ARRAY_SIZE
1620 095d0ed3 2024-10-05 benni CALL PROC_N 1 ─────────► PROC_N+1
1621 095d0ed3 2024-10-05 benni ◄───────┐ PUSH BP
1622 095d0ed3 2024-10-05 benni │ PUSH CX
1623 095d0ed3 2024-10-05 benni │ MOVE BP, SP
1624 095d0ed3 2024-10-05 benni │ SUB SP, WORK_SPACE
1628 095d0ed3 2024-10-05 benni │ "PROCEDURE BODY"
1632 095d0ed3 2024-10-05 benni │ MOV SP, BP
1638 095d0ed3 2024-10-05 benni ╠═════════════╣─┐
1639 095d0ed3 2024-10-05 benni ║ PARAMETERS ║ │
1640 095d0ed3 2024-10-05 benni ╟─────────────╢ │
1641 095d0ed3 2024-10-05 benni ║ RETURN ADDR ║ │
1642 095d0ed3 2024-10-05 benni ╟─────────────╢ ├─PROCEDURE N
1643 095d0ed3 2024-10-05 benni ╔ ═ ═╗ ║ REGISTERS ║ │ STACK FRAME
1644 095d0ed3 2024-10-05 benni BP ─────────►╟─────────────╢ │
1645 095d0ed3 2024-10-05 benni ╚═ ═ ╝ ║ ║ │ PROCEDURE
1646 095d0ed3 2024-10-05 benni ▲ ║ WORK_SPACE ║ │ N+1 STACK
1647 095d0ed3 2024-10-05 benni BOTTOM │ ╟─────────────╢═╡ FRAME
1648 095d0ed3 2024-10-05 benni OF │ ║ PARAMETERS ║ ├──────┘
1649 095d0ed3 2024-10-05 benni STACK │ ╟─────────────╢ │ DYNAMICALLY
1650 095d0ed3 2024-10-05 benni ║ RETURN ADDR ║ │ ALLOCATED
1651 095d0ed3 2024-10-05 benni ╟─────────────╢ │ ON DEMAND
1652 095d0ed3 2024-10-05 benni ╔════╗ ║ REGISTERS ║ │ RATHER THAN
1653 095d0ed3 2024-10-05 benni ║ BP ╟─────────►╟─────────────╢ │┐STATICALLY
1654 095d0ed3 2024-10-05 benni ╚════╝ ║ ║ │├─────┘
1655 095d0ed3 2024-10-05 benni ║ WORK_SPACE ║ ││
1656 095d0ed3 2024-10-05 benni ┌─ ── ── ── ─►╟─────────────╢─┘┘ ◄───┐
1657 095d0ed3 2024-10-05 benni ├─ ── ── ── ─►║ ║ TOP OF STACK
1658 095d0ed3 2024-10-05 benni ╔══════╤═══╧══╗ ║ ║
1659 095d0ed3 2024-10-05 benni ║ SS │ SP ║ ╚═════════════╝ STACK SEGMENT BASE
1660 095d0ed3 2024-10-05 benni ╚══════╧══════╝
1663 095d0ed3 2024-10-05 benni 2.3.4 Status and Control Registers
1665 095d0ed3 2024-10-05 benni Two status and control registers are of immediate concern to applications
1666 095d0ed3 2024-10-05 benni programmers: the instruction pointer and the FLAGS registers.
1668 095d0ed3 2024-10-05 benni The instruction pointer register (IP) contains the offset address, relative
1669 095d0ed3 2024-10-05 benni to the start of the current code segment, of the next sequential instruction
1670 095d0ed3 2024-10-05 benni to be executed. Together, the CS:IP registers thus define a 32-bit
1671 095d0ed3 2024-10-05 benni program-counter. The instruction pointer is not directly visible to the
1672 095d0ed3 2024-10-05 benni programmer; it is controlled implicitly, by interrupts, traps, and
1673 095d0ed3 2024-10-05 benni control-transfer operations.
1675 095d0ed3 2024-10-05 benni The FLAGS register encompasses eleven flag fields, mostly one-bit wide, as
1676 095d0ed3 2024-10-05 benni shown in figure 2-10. Six of the flags are status flags that record
1677 095d0ed3 2024-10-05 benni processor status information. The status flags are affected by the execution
1678 095d0ed3 2024-10-05 benni of arithmetic and logical instructions. The carry flag is also modifiable
1679 095d0ed3 2024-10-05 benni with instructions that will clear, set or complement this flag bit. See
1680 095d0ed3 2024-10-05 benni Chapters 3 and 4.
1682 095d0ed3 2024-10-05 benni The carry flag (CF) generally indicates a carry or borrow out of the most
1683 095d0ed3 2024-10-05 benni significant bit of an 8- or 16-bit operand after performing an arithmetic
1684 095d0ed3 2024-10-05 benni operation; this flag is also useful for bit manipulation operations
1685 095d0ed3 2024-10-05 benni involving the shift and rotate instructions. The effect on the remaining
1686 095d0ed3 2024-10-05 benni status flags, when defined for a particular instruction, is generally as
1687 095d0ed3 2024-10-05 benni follows: the zero flag (ZF) indicates a zero result when set; the sign flag
1688 095d0ed3 2024-10-05 benni (SF) indicates whether the result was negative (SF=1) or positive (SF=0);
1689 095d0ed3 2024-10-05 benni when set, the overflow flag (OF) indicates whether an operation results in
1690 095d0ed3 2024-10-05 benni a carry into the high order bit of the result but not a carry out of the
1691 095d0ed3 2024-10-05 benni high-order bit, or vice versa; the parity flag (PF) indicates whether the
1692 095d0ed3 2024-10-05 benni modulo 2 sum of the low-order eight bits of the operation is even (PF=0) or
1693 095d0ed3 2024-10-05 benni odd (PF=1) parity. The auxiliary carry flag (AF) represents a carry out of
1694 095d0ed3 2024-10-05 benni or borrow into the least significant 4-bit digit when performing binary
1695 095d0ed3 2024-10-05 benni coded decimal (BCD) arithmetic.
1697 095d0ed3 2024-10-05 benni The FLAGS register also contains three control flags that are used, under
1698 095d0ed3 2024-10-05 benni program control, to direct certain processor operations. The
1699 095d0ed3 2024-10-05 benni interrupt-enable flag (IF), if set, enables external interrupts; otherwise,
1700 095d0ed3 2024-10-05 benni interrupts are disabled. The trap flag (TF), if set, puts the processor
1701 095d0ed3 2024-10-05 benni into a single-step mode for debugging purposes where the target program is
1702 095d0ed3 2024-10-05 benni automatically interrupted to a user supplied debug routine after the
1703 095d0ed3 2024-10-05 benni execution of each target program instruction. The direction flag (DF)
1704 095d0ed3 2024-10-05 benni controls the forward or backward direction of string operations: 0 = forward
1705 095d0ed3 2024-10-05 benni or auto increment the address register(s) (SI, DI or SI and DI),
1706 095d0ed3 2024-10-05 benni 1 = backward or auto-decrement the address register(s) (SI, DI or SI
1709 095d0ed3 2024-10-05 benni In general, the interrupt enable flag may be set or reset with special
1710 095d0ed3 2024-10-05 benni instructions (STI = set, CLI = clear) or by placing the flags on the stack,
1711 095d0ed3 2024-10-05 benni modifying the stack, and returning the flag image from the stack to the flag
1712 095d0ed3 2024-10-05 benni register. If operating in Protected Mode, the ability to alter the IF bit
1713 095d0ed3 2024-10-05 benni is subject to protection checks to prevent non-privileged programs from
1714 095d0ed3 2024-10-05 benni effecting the interrupt state of the CPU. This applies to both instruction
1715 095d0ed3 2024-10-05 benni and stack options for modifying the IF bit.
1717 095d0ed3 2024-10-05 benni The TF flag may only be modified by copying the flag register to the stack,
1718 095d0ed3 2024-10-05 benni setting the TF bit in the stack image, and returning the modified stack
1719 095d0ed3 2024-10-05 benni image to the flag register. The trap interrupt occurs on completion of the
1720 095d0ed3 2024-10-05 benni next instruction. Entry to the single step routine saves the flag register
1721 095d0ed3 2024-10-05 benni on the stack with the TF bit set, and resets the TF bit in the register.
1722 095d0ed3 2024-10-05 benni After completion of the single step routine, the TF bit is automatically set
1723 095d0ed3 2024-10-05 benni on return to the program being single stepped to interrupt the program again
1724 095d0ed3 2024-10-05 benni after completion of the next instruction. Use of TF is not inhibited by the
1725 095d0ed3 2024-10-05 benni protection mechanism in Protected Mode.
1727 095d0ed3 2024-10-05 benni The DF flag, like the IF flag, is controlled by instructions (CLD = clear,
1728 095d0ed3 2024-10-05 benni STD = set) or flag register modification through the stack. Typically,
1729 095d0ed3 2024-10-05 benni routines that use string instructions will save the flags on the stack,
1730 095d0ed3 2024-10-05 benni modify DF as necessary via the instructions provided, and restore DF to its
1731 095d0ed3 2024-10-05 benni original state by restoring the Flag register from the stack before
1732 095d0ed3 2024-10-05 benni returning. Access or control of the DF flag is not inhibited by the
1733 095d0ed3 2024-10-05 benni protection mechanism in Protected Mode.
1735 095d0ed3 2024-10-05 benni The Special Fields bits are only relevant in Protected Mode. Real Address
1736 095d0ed3 2024-10-05 benni Mode programs should treat these bits as don't-care's, making no assumption
1737 095d0ed3 2024-10-05 benni about their status. Attempts to modify the IOPL and NT fields are subject to
1738 095d0ed3 2024-10-05 benni protection checking in Protected Mode. In general, the application's
1739 095d0ed3 2024-10-05 benni programmer will not be able to and should not attempt to modify these bits.
1740 095d0ed3 2024-10-05 benni (See section 10.3, "Privileged and Trusted Instructions" for more details.)
1743 095d0ed3 2024-10-05 benni Figure 2-10. Flags Register
1745 095d0ed3 2024-10-05 benni STATUS FLAGS:
1746 095d0ed3 2024-10-05 benni CARRY────────────────────────────────────────────────┐
1747 095d0ed3 2024-10-05 benni PARITY─────────────────────────────────────────┐ │
1748 095d0ed3 2024-10-05 benni AUXILLIARY CARRY─────────────────────────┐ │ │
1749 095d0ed3 2024-10-05 benni ZERO───────────────────────────────┐ │ │ │
1750 095d0ed3 2024-10-05 benni SIGN────────────────────────────┐ │ │ │ │
1751 095d0ed3 2024-10-05 benni OVERFLOW────────────┐ │ │ │ │ │
1752 095d0ed3 2024-10-05 benni │ │ │ │ │ │
1753 095d0ed3 2024-10-05 benni 15 14 13 12▼11 10 9 8▼ 7▼ 6 5▼ 4 3▼ 2 1▼ 0
1754 095d0ed3 2024-10-05 benni ╔══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╗
1755 095d0ed3 2024-10-05 benni FLAGS:║▒▒│NT│IOPL │OF│DF│IF│TF│SF│ZF│▒▒│AF│▒▒│PF│▒▒│CF║
1756 095d0ed3 2024-10-05 benni ╚══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╝
1757 095d0ed3 2024-10-05 benni ▲ ▲ ▲ ▲ ▲
1758 095d0ed3 2024-10-05 benni │ │ │ │ │ CONTROL FLAGS:
1759 095d0ed3 2024-10-05 benni │ │ │ │ └───────────TRAP FLAG
1760 095d0ed3 2024-10-05 benni │ │ │ └──────────────INTERRUPT ENABLE
1761 095d0ed3 2024-10-05 benni │ │ └─────────────────DIRECTION FLAG
1762 095d0ed3 2024-10-05 benni │ │ SPECIAL FIELDS:
1763 095d0ed3 2024-10-05 benni │ └─────────────────────────I/O PRIVILEGE LEVEL
1764 095d0ed3 2024-10-05 benni └─────────────────────────────NESTED TASK FLAG
1767 095d0ed3 2024-10-05 benni 2.4 Addressing Modes
1769 095d0ed3 2024-10-05 benni The information encoded in an 80286 instruction includes a specification of
1770 095d0ed3 2024-10-05 benni the operation to be performed, the type of the operands to be manipulated,
1771 095d0ed3 2024-10-05 benni and the location of these operands. If an operand is located in memory, the
1772 095d0ed3 2024-10-05 benni instruction must also select, explicitly or implicitly, which of the
1773 095d0ed3 2024-10-05 benni currently addressable segments contains the operand. This section covers the
1774 095d0ed3 2024-10-05 benni operand addressing mechanisms; 80286 operators are discussed in Chapter 3.
1776 095d0ed3 2024-10-05 benni The five elements of a general instruction are briefly described below. The
1777 095d0ed3 2024-10-05 benni exact format of 80286 instructions is specified in Appendix B.
1779 095d0ed3 2024-10-05 benni ■ The opcode is present in all instructions; in fact, it is the only
1780 095d0ed3 2024-10-05 benni required element. Its principal function is the specification of the
1781 095d0ed3 2024-10-05 benni operation performed by the instruction.
1783 095d0ed3 2024-10-05 benni ■ A register specifier.
1785 095d0ed3 2024-10-05 benni ■ The addressing mode specifier, when present, is used to specify the
1786 095d0ed3 2024-10-05 benni addressing mode of an operand for referencing data or performing
1787 095d0ed3 2024-10-05 benni indirect calls or jumps.
1789 095d0ed3 2024-10-05 benni ■ The displacement, when present, is used to compute the effective
1790 095d0ed3 2024-10-05 benni address of an operand in memory.
1792 095d0ed3 2024-10-05 benni ■ The immediate operand, when present, directly specifies one operand of
1793 095d0ed3 2024-10-05 benni the instruction.
1795 095d0ed3 2024-10-05 benni Of the four elements, only one, the opcode, is always present. The other
1796 095d0ed3 2024-10-05 benni elements may or may not be present, depending on the particular operation
1797 095d0ed3 2024-10-05 benni involved and on the location and type of the operands.
1800 095d0ed3 2024-10-05 benni 2.4.1 Operands
1802 095d0ed3 2024-10-05 benni Generally speaking, an instruction is an operation performed on zero, one,
1803 095d0ed3 2024-10-05 benni or two operands, which are the data manipulated by the instruction. An
1804 095d0ed3 2024-10-05 benni operand can be located either in a register (AX, BX, CX, DX, SI, DI, SP, or
1805 095d0ed3 2024-10-05 benni BP in the case of 16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the
1806 095d0ed3 2024-10-05 benni case of 8-bit operands; the FLAG register for flag operations in the
1807 095d0ed3 2024-10-05 benni instruction itself (as an immediate operand)), or in memory or an I/O port.
1808 095d0ed3 2024-10-05 benni Immediate operands and operands in registers can be accessed more rapidly
1809 095d0ed3 2024-10-05 benni than operands in memory since memory operands must be fetched from memory
1810 095d0ed3 2024-10-05 benni while immediate and register operands are available in the processor.
1812 095d0ed3 2024-10-05 benni An 80286 instruction can reference zero, one, or two operands. The three
1813 095d0ed3 2024-10-05 benni forms are as follows:
1815 095d0ed3 2024-10-05 benni ■ Zero-operand instructions, such as RET, NOP, and HLT. Consult Appendix
1818 095d0ed3 2024-10-05 benni ■ One-operand instructions, such as INC or DEC. The location of the
1819 095d0ed3 2024-10-05 benni single operand can be specified implicitly, as in AAM (where the
1820 095d0ed3 2024-10-05 benni register AX contains the operand), or explicitly, as in INC (where
1821 095d0ed3 2024-10-05 benni the operand can be in any register or memory location). Explicitly
1822 095d0ed3 2024-10-05 benni specified operands are accessed via one of the addressing modes
1823 095d0ed3 2024-10-05 benni described in section 2.4.2.
1825 095d0ed3 2024-10-05 benni ■ Two operand instructions such as MOV, ADD, XOR, etc., generally
1826 095d0ed3 2024-10-05 benni overwrite one of the two participating operands with the result. A
1827 095d0ed3 2024-10-05 benni distinction can thus be made between the source operand (the one left
1828 095d0ed3 2024-10-05 benni unaffected by the operation) and the destination operand (the one
1829 095d0ed3 2024-10-05 benni overwritten by the result). Like one-operand instructions, two-operand
1830 095d0ed3 2024-10-05 benni instructions can specify the location of operands either explicitly or
1831 095d0ed3 2024-10-05 benni implicitly. If an instruction contains two explicitly specified
1832 095d0ed3 2024-10-05 benni operands, only one of them──either the source or the destination──can
1833 095d0ed3 2024-10-05 benni be in a register or memory location. The other operand must be in a
1834 095d0ed3 2024-10-05 benni register or be an immediate source operand. Special cases of
1835 095d0ed3 2024-10-05 benni two-operand instructions are the string instructions and stack
1836 095d0ed3 2024-10-05 benni manipulation. Both operands of some string instructions are in memory
1837 095d0ed3 2024-10-05 benni and are explicitly specified. Push and pop stack operations allow
1838 095d0ed3 2024-10-05 benni transfer between memory operands and the memory based stack.
1840 095d0ed3 2024-10-05 benni Thus, the two-operand instructions of the 80286 permit operations of the
1841 095d0ed3 2024-10-05 benni following sort:
1843 095d0ed3 2024-10-05 benni ■ Register-to-register
1844 095d0ed3 2024-10-05 benni ■ Register-to-memory
1845 095d0ed3 2024-10-05 benni ■ Memory-to-register
1846 095d0ed3 2024-10-05 benni ■ Immediate-to-register
1847 095d0ed3 2024-10-05 benni ■ Immediate-to-memory
1848 095d0ed3 2024-10-05 benni ■ Memory-to-memory
1850 095d0ed3 2024-10-05 benni Instructions can specify the location of their operands by means of eight
1851 095d0ed3 2024-10-05 benni addressing modes, which are described in sections 2.4.2 and 2.4.3.
1854 095d0ed3 2024-10-05 benni 2.4.2 Register and Immediate Modes
1856 095d0ed3 2024-10-05 benni Two addressing modes are used to reference operands contained in registers
1857 095d0ed3 2024-10-05 benni and instructions:
1859 095d0ed3 2024-10-05 benni ■ Register Operand Mode. The operand is located in one of the 16-bit
1860 095d0ed3 2024-10-05 benni registers (AX, BX, CX, DX, SI, DI, SP, or BP) or in one of the 8-bit
1861 095d0ed3 2024-10-05 benni general registers (AH, BH, CH, DH, AL, BL, CL, or DL).
1863 095d0ed3 2024-10-05 benni Special instructions are also included for referencing the CS, DS, ES, SS,
1864 095d0ed3 2024-10-05 benni and Flag registers as operands also.
1866 095d0ed3 2024-10-05 benni ■ Immediate Operand Mode. The operand is part of the instruction itself
1867 095d0ed3 2024-10-05 benni (the immediate operand element).
1870 095d0ed3 2024-10-05 benni 2.4.3 Memory Addressing Modes
1872 095d0ed3 2024-10-05 benni Six modes are used to access operands in memory. Memory operands are
1873 095d0ed3 2024-10-05 benni accessed by means of a pointer consisting of a segment selector (see section
1874 095d0ed3 2024-10-05 benni 2.3.2) and an offset, which specifies the operand's displacement in bytes
1875 095d0ed3 2024-10-05 benni from the beginning of the segment in which it resides. Both the segment
1876 095d0ed3 2024-10-05 benni selector component and the offset component are 16-bit values. (See section
1877 095d0ed3 2024-10-05 benni 2.1 for a discussion of segmentation.) Only some instructions use a full
1878 095d0ed3 2024-10-05 benni 32-bit address.
1880 095d0ed3 2024-10-05 benni Most memory references do not require the instruction to specify a full
1881 095d0ed3 2024-10-05 benni 32-bit pointer address. Operands that are located within one of the
1882 095d0ed3 2024-10-05 benni currently addressable segments, as determined by the four segment registers
1883 095d0ed3 2024-10-05 benni (see section 2.3.2, "Segment Registers"), can be referenced very
1884 095d0ed3 2024-10-05 benni efficiently simply by means of the 16-bit offset. This form of address is
1885 095d0ed3 2024-10-05 benni called by short address. The choice of segment (CS, DS, ES, or SS) is either
1886 095d0ed3 2024-10-05 benni implicit within the instruction itself or explicitly specified by means of
1887 095d0ed3 2024-10-05 benni a segment override prefix (see below).
1889 095d0ed3 2024-10-05 benni See figure 2-11 for a diagram of the addressing process.
1892 095d0ed3 2024-10-05 benni 2.4.3.1 Segment Selection
1894 095d0ed3 2024-10-05 benni All instructions that address operands in memory must specify the segment
1895 095d0ed3 2024-10-05 benni and the offset. For speed and compact instruction encoding, segment
1896 095d0ed3 2024-10-05 benni selectors are usually stored in the high speed segment registers. An
1897 095d0ed3 2024-10-05 benni instruction need specify only the desired segment register and an offset in
1898 095d0ed3 2024-10-05 benni order to address a memory operand.
1900 095d0ed3 2024-10-05 benni Most instructions need not explicitly specify which segment register is
1901 095d0ed3 2024-10-05 benni used. The correct segment register is automatically chosen according to the
1902 095d0ed3 2024-10-05 benni rules of table 2-1 and table 2-2. These rules follow the way programs are
1903 095d0ed3 2024-10-05 benni written (see figure 2-12) as independent modules that require areas for
1904 095d0ed3 2024-10-05 benni code and data, a stack, and access to external data areas.
1906 095d0ed3 2024-10-05 benni There is a close connection between the type of memory reference and the
1907 095d0ed3 2024-10-05 benni segment in which that operand resides (see the next section for a
1908 095d0ed3 2024-10-05 benni discussion of how memory addressing mode calculations are performed). As a
1909 095d0ed3 2024-10-05 benni rule, a memory reference implies the current data segment (i.e., the
1910 095d0ed3 2024-10-05 benni implicit segment selector is in DS) unless the BP register is involved in
1911 095d0ed3 2024-10-05 benni the address specification, in which case the current stack segment is
1912 095d0ed3 2024-10-05 benni implied (i.e, SS contains the selector).
1914 095d0ed3 2024-10-05 benni The 80286 instruction set defines special instruction prefix elements (see
1915 095d0ed3 2024-10-05 benni Appendix B). One of these is SEG, the segment-override prefix.
1916 095d0ed3 2024-10-05 benni Segment-override prefixes allow an explicit segment selection. Only in two
1917 095d0ed3 2024-10-05 benni special cases──namely, the use of DI to reference destination strings in
1918 095d0ed3 2024-10-05 benni the ES segment, and the use of SP to reference stack locations in the SS
1919 095d0ed3 2024-10-05 benni segment──is there an implied segment selection which cannot be overridden.
1920 095d0ed3 2024-10-05 benni The format of segment override prefixes is shown in Appendix B.
1923 095d0ed3 2024-10-05 benni Table 2-2 Segment Register Selection Rules
1925 095d0ed3 2024-10-05 benni Memory Reference Segment Register Implicit Segment
1926 095d0ed3 2024-10-05 benni Needed Used Selection Rule
1928 095d0ed3 2024-10-05 benni Instructions Code (CS) Automatic with
1929 095d0ed3 2024-10-05 benni instruction prefetch.
1931 095d0ed3 2024-10-05 benni Stack Stack (SS) All stack pushes and
1932 095d0ed3 2024-10-05 benni pops. Any memory reference
1933 095d0ed3 2024-10-05 benni which uses BP as a base
1934 095d0ed3 2024-10-05 benni register.
1936 095d0ed3 2024-10-05 benni Local Data Data (DS) All data references
1937 095d0ed3 2024-10-05 benni except when relative to
1938 095d0ed3 2024-10-05 benni stack or string destination.
1940 095d0ed3 2024-10-05 benni External (Global) Extra (ES) Alternate data segment
1941 095d0ed3 2024-10-05 benni Data and destination of string
1942 095d0ed3 2024-10-05 benni operation.
1945 095d0ed3 2024-10-05 benni Figure 2-11. Two-Component Address
1948 095d0ed3 2024-10-05 benni POINTER ║ ║
1949 095d0ed3 2024-10-05 benni ┌───────────┴───────────┐ ╠═════════════╣─┐
1950 095d0ed3 2024-10-05 benni ╔═══════════╤═══════════╗ ║ ║ │
1951 095d0ed3 2024-10-05 benni ║ SEGMENT │ OFFSET ║ ║ ║ │
1952 095d0ed3 2024-10-05 benni ╚═══════════╧═══════════╝ ║ ║ │
1953 095d0ed3 2024-10-05 benni 31 16 15 0 ╟─────────────╢ │
1954 095d0ed3 2024-10-05 benni └────┬────┘ └────┬────┘ ║ OPERAND ║ │ SELECTED
1955 095d0ed3 2024-10-05 benni │ │ ║ SELECTED ║ ├─ SEGMENT
1956 095d0ed3 2024-10-05 benni │ └───────────────────►╟─────────────╢ │
1961 095d0ed3 2024-10-05 benni └───────────────────────────────►╠═════════════╣─┘
1963 095d0ed3 2024-10-05 benni • MEMORY •
1966 095d0ed3 2024-10-05 benni 2.4.3.2 Offset Computation
1968 095d0ed3 2024-10-05 benni The offset within the desired segment is calculated in accordance with the
1969 095d0ed3 2024-10-05 benni desired addressing mode. The offset is calculated by taking the sum of up to
1970 095d0ed3 2024-10-05 benni three components:
1972 095d0ed3 2024-10-05 benni ■ the displacement element in the instruction
1973 095d0ed3 2024-10-05 benni ■ the base (contents of BX or BP──a base register)
1974 095d0ed3 2024-10-05 benni ■ the index (contents of SI or DI──an index register)
1976 095d0ed3 2024-10-05 benni Each of the three components of an offset may be either a positive or
1977 095d0ed3 2024-10-05 benni negative value. Offsets are calculated modulo 2^(16).
1979 095d0ed3 2024-10-05 benni The six memory addressing modes are generated using various combinations of
1980 095d0ed3 2024-10-05 benni these three components. The six modes are used for accessing different types
1981 095d0ed3 2024-10-05 benni of data stored in memory:
1983 095d0ed3 2024-10-05 benni addressing mode offset calculation
1984 095d0ed3 2024-10-05 benni direct address displacement alone
1985 095d0ed3 2024-10-05 benni register indirect base or index alone
1986 095d0ed3 2024-10-05 benni based base + displacement
1987 095d0ed3 2024-10-05 benni indexed index + displacement
1988 095d0ed3 2024-10-05 benni based indexed base + index
1989 095d0ed3 2024-10-05 benni based indexed with displacement base + index + disp
1991 095d0ed3 2024-10-05 benni In all six modes, the operand is located at the specified offset within the
1992 095d0ed3 2024-10-05 benni selected segment. All displacements, except direct address mode, are
1993 095d0ed3 2024-10-05 benni optionally 8- or 16-bit values. 8-bit displacements are automatically
1994 095d0ed3 2024-10-05 benni sign-extended to 16 bits. The six addressing modes are described and
1995 095d0ed3 2024-10-05 benni demonstrated in the following section on memory addressing modes.
1998 095d0ed3 2024-10-05 benni Figure 2-12. Use of Memory Segmentation
2003 095d0ed3 2024-10-05 benni ╟──────╢ MODULE A
2007 095d0ed3 2024-10-05 benni ┌───────────┐ ╔══════╗
2008 095d0ed3 2024-10-05 benni │ ╔═══════╗ │ ║ CODE ║
2009 095d0ed3 2024-10-05 benni │ ║ CODE ╟─┼─────────────────────────►╟──────╢ MODULE B
2010 095d0ed3 2024-10-05 benni │ ╟───────╢ │ ║ DATA ║
2011 095d0ed3 2024-10-05 benni │ ║ DATA ╟─┼─────────────────────────►╚══════╝
2012 095d0ed3 2024-10-05 benni │ ╟───────╢ │ │ │
2013 095d0ed3 2024-10-05 benni │ ║ STACK ╟─┼───────────────┐ ╔══════╗
2014 095d0ed3 2024-10-05 benni │ ╟───────╢ │ │ ║ ║ PROCESS STACK
2015 095d0ed3 2024-10-05 benni │ ║ EXTRA ╟─┼───────────┐ └─────────►╚══════╝
2016 095d0ed3 2024-10-05 benni │ ╚═══════╝ │ │ │ │
2017 095d0ed3 2024-10-05 benni │ SEGMENT │ │ ╔══════╗ PROCESS
2018 095d0ed3 2024-10-05 benni │ REGISTERS │ │ ║ ║ DATA
2019 095d0ed3 2024-10-05 benni └───────────┘ └─────────────►╚══════╝ BLOCK 1
2021 095d0ed3 2024-10-05 benni ╔══════╗ PROCESS
2023 095d0ed3 2024-10-05 benni ╚══════╝ BLOCK 2
2028 095d0ed3 2024-10-05 benni 2.4.3.3 Memory Mode
2030 095d0ed3 2024-10-05 benni Two modes are used for simple scalar operands located in memory:
2032 095d0ed3 2024-10-05 benni ■ Direct Address Mode. The offset of the operand is contained in the
2033 095d0ed3 2024-10-05 benni instruction as the displacement element. The offset is a 16-bit
2034 095d0ed3 2024-10-05 benni quantity.
2036 095d0ed3 2024-10-05 benni ■ Register Indirect Mode. The offset of the operand is in one of the
2037 095d0ed3 2024-10-05 benni registers SI, DI, or BX. (BP is excluded; if BP is used as a stack
2038 095d0ed3 2024-10-05 benni frame base, it requires an index or displacement component to reference
2039 095d0ed3 2024-10-05 benni either parameters passed on the stack or temporary variables allocated
2040 095d0ed3 2024-10-05 benni on the stack. The instruction level bit encoding for the BP only
2041 095d0ed3 2024-10-05 benni address mode is used to specify Direct Address mode.)
2043 095d0ed3 2024-10-05 benni The following four modes are used for accessing complex data structures in
2044 095d0ed3 2024-10-05 benni memory (see figure 2-13):
2046 095d0ed3 2024-10-05 benni ■ Based Mode. The operand is located within the selected segment at an
2047 095d0ed3 2024-10-05 benni offset computed as the sum of the displacement and the contents of a
2048 095d0ed3 2024-10-05 benni base register (BX or BP). Based mode is often used to access the same
2049 095d0ed3 2024-10-05 benni field in different copies of a structure (often called a record). The
2050 095d0ed3 2024-10-05 benni base register points to the base of the structure (hence the term
2051 095d0ed3 2024-10-05 benni "base" register), and the displacement selects a particular field.
2052 095d0ed3 2024-10-05 benni Corresponding fields within a collection of structures can be accessed
2053 095d0ed3 2024-10-05 benni simply by changing the base register. (See figure 2-13, example 1.)
2055 095d0ed3 2024-10-05 benni ■ Indexed Mode. The operand is located within the selected segment at an
2056 095d0ed3 2024-10-05 benni offset computed as the sum of the displacement and the contents of an
2057 095d0ed3 2024-10-05 benni index register (SI or DI). Indexed mode is often used to access
2058 095d0ed3 2024-10-05 benni elements in a static array (e.g., an array whose starting location is
2059 095d0ed3 2024-10-05 benni fixed at translation time). The displacement locates the beginning of
2060 095d0ed3 2024-10-05 benni the array, and the value of the index register selects one element.
2061 095d0ed3 2024-10-05 benni Since all array elements are the same length, simple arithmetic on the
2062 095d0ed3 2024-10-05 benni index register will select any element. (See figure 2-13, example 2.)
2064 095d0ed3 2024-10-05 benni ■ Based Indexed Mode. The operand is located within the selected segment
2065 095d0ed3 2024-10-05 benni at an offset computed as the sum of the base register's contents and an
2066 095d0ed3 2024-10-05 benni index register's contents. Based Indexed mode is often used to access
2067 095d0ed3 2024-10-05 benni elements of a dynamic array (i.e., an array whose base address can
2068 095d0ed3 2024-10-05 benni change during execution). The base register points to the base of the
2069 095d0ed3 2024-10-05 benni array, and the value of the index register is used to select one
2070 095d0ed3 2024-10-05 benni element. (See figure 2-13, example 3.)
2072 095d0ed3 2024-10-05 benni ■ Based Indexed Mode with Displacement. The operand is located with the
2073 095d0ed3 2024-10-05 benni selected segment at an offset computed as the sum of a base register's
2074 095d0ed3 2024-10-05 benni contents, an index register's contents, and the displacement. This mode
2075 095d0ed3 2024-10-05 benni is often used to access elements of an array within a structure. For
2076 095d0ed3 2024-10-05 benni example, the structure could be an activation record (i.e., a region
2077 095d0ed3 2024-10-05 benni of the stack containing the register contents, parameters, and
2078 095d0ed3 2024-10-05 benni variables associated with one instance of a procedure); and one
2079 095d0ed3 2024-10-05 benni variable could be an array. The base register points to the start of
2080 095d0ed3 2024-10-05 benni the activation record, the displacement expresses the distance from the
2081 095d0ed3 2024-10-05 benni start of the record to the beginning of the array variable, and the
2082 095d0ed3 2024-10-05 benni index register selects a particular element of the array. (See figure
2083 095d0ed3 2024-10-05 benni 2-13, example 4.)
2085 095d0ed3 2024-10-05 benni Table 2-3 gives a summary of all memory operand addressing options.
2088 095d0ed3 2024-10-05 benni Table 2-3. Memory Operand Addressing Modes
2090 095d0ed3 2024-10-05 benni Addressing Mode Offset Calculation
2092 095d0ed3 2024-10-05 benni Direct 16-bit Displacement in the instruction
2093 095d0ed3 2024-10-05 benni Register Indirect BX, SI, DI
2094 095d0ed3 2024-10-05 benni Based (BX or BP) + Displacement
2095 095d0ed3 2024-10-05 benni The displacement can be a 0, 8 or 16-bit value.
2096 095d0ed3 2024-10-05 benni Indexed (SI or DI) + Displacement
2097 095d0ed3 2024-10-05 benni The displacement can be a 0, 8 or 16-bit value.
2098 095d0ed3 2024-10-05 benni Based Indexed (BX or BP) + (SI or DI)
2099 095d0ed3 2024-10-05 benni Based Indexed + Displacement (BX or BP) + (SI or DI) + Displacement
2100 095d0ed3 2024-10-05 benni The displacement can be a 0, 8 or 16-bit value.
2103 095d0ed3 2024-10-05 benni Figure 2-13. Complex Addressing Modes
2105 095d0ed3 2024-10-05 benni 1. BASED MODE 2. INDEXED MODE
2107 095d0ed3 2024-10-05 benni MOV AX, [BP + DATE_CODE] MOV ID[SI], DX
2108 095d0ed3 2024-10-05 benni ADD[BX + BALANCE], CX SUB BX, DATA_TBL[SI]
2110 095d0ed3 2024-10-05 benni • • • • F
2111 095d0ed3 2024-10-05 benni ╠═══════════╣─┐ ╠═══════════╣─┐ I
2112 095d0ed3 2024-10-05 benni ║ ║ │ ║ ║ │ X
2113 095d0ed3 2024-10-05 benni ╔═══════════╗ ╟───────────╢ │ ╔═══════════╗ ╟───────────╢ │ E
2114 095d0ed3 2024-10-05 benni ║ DISPL ╟────►║ OPERAND ║ ├─ ║ INDEX ╟────►║ OPERAND ║ ├─D
2115 095d0ed3 2024-10-05 benni ╚═══════════╝ ╟───────────╢ │ ╚═══════════╝ ╟───────────╢ │
2116 095d0ed3 2024-10-05 benni + ║ ║ │ + ║ ║ │ A
2117 095d0ed3 2024-10-05 benni ╔═══════════╗ ┌──►╟───────────╢─┘ ╔═══════════╗ ┌──►╟───────────╢─┘ R
2118 095d0ed3 2024-10-05 benni ║ BASE ╟─┘ ║ ║ ║ DISPL ╟─┘ ║ ║ R
2119 095d0ed3 2024-10-05 benni ╚═══════════╝ ║ ║ ╚═══════════╝ ║ ║ A
2120 095d0ed3 2024-10-05 benni + ║ ║ + ║ ║ Y
2121 095d0ed3 2024-10-05 benni ╔═══════════╗ ║ ║ ╔═══════════╗ ║ ║
2122 095d0ed3 2024-10-05 benni ║ SEGMENT ╟────►╚═══════════╝ ║ SEGMENT ╟────►╚═══════════╝
2123 095d0ed3 2024-10-05 benni ╚═══════════╝ ╚═══════════╝
2125 095d0ed3 2024-10-05 benni 3. BASED INDEXED 4. BASED INDEXED MODE
2126 095d0ed3 2024-10-05 benni WITH DISPLACEMENT BASED
2127 095d0ed3 2024-10-05 benni MOV DX, [BP][DI] STRUCTURE
2128 095d0ed3 2024-10-05 benni AND [BX + SI], 3FFH MOV CX, [BP][SI + CNT] CONTAINING
2129 095d0ed3 2024-10-05 benni SHR[BX + DI + MASK] ARRAY
2130 095d0ed3 2024-10-05 benni • • B • • └─┐
2131 095d0ed3 2024-10-05 benni ╠═══════════╣─┐ A ╠═══════════╣ ──┐│
2132 095d0ed3 2024-10-05 benni ║ ║ │ S ║ ║ ││
2133 095d0ed3 2024-10-05 benni ╔═══════════╗ ╟───────────╢ │ E ╔═══════════╗ ╟───────────╢─┐ ││
2134 095d0ed3 2024-10-05 benni ║ INDEX ╟────►║ OPERAND ║ ├─D ║ INDEX ╟───┐ ║▒▒▒▒▒▒▒▒▒▒▒║ │ A ││
2135 095d0ed3 2024-10-05 benni ╚═══════════╝ ╟───────────╢ │ ╚═══════════╝ │ ╟───────────╢ │ R ││
2136 095d0ed3 2024-10-05 benni + ║ ║ │ A + └►║ OPERAND ║ ├─R ├┘
2137 095d0ed3 2024-10-05 benni ╔═══════════╗ ┌──►╟───────────╢─┘ R ╔═══════════╗ ┌──►╟───────────╢ │ A │
2138 095d0ed3 2024-10-05 benni ║ BASE ╟─┘ ║ ║ R ║ DISPL ╟─┘ ║▒▒▒▒▒▒▒▒▒▒▒║ │ Y │
2139 095d0ed3 2024-10-05 benni ╚═══════════╝ ║ ║ A ╚═══════════╝ ┌►╟───────────╢─┘ │
2140 095d0ed3 2024-10-05 benni + ║ ║ Y + │ ║ ║ │
2141 095d0ed3 2024-10-05 benni ╔═══════════╗ ║ ║ ╔═══════════╗ │ ╟───────────╢ ──┘
2142 095d0ed3 2024-10-05 benni ║ SEGMENT ╟────►╚═══════════╝ ║ BASE ╟───┘ ║ ║
2143 095d0ed3 2024-10-05 benni ╚═══════════╝ ╚═══════════╝ ║ ║
2145 095d0ed3 2024-10-05 benni ╔═══════════╗ ║ ║
2146 095d0ed3 2024-10-05 benni ║ SEGMENT ╟────►╚═══════════╝
2147 095d0ed3 2024-10-05 benni ╚═══════════╝
2150 095d0ed3 2024-10-05 benni 2.5 Input/Output
2152 095d0ed3 2024-10-05 benni The 80286 allows input/output to be performed in either of two ways: by
2153 095d0ed3 2024-10-05 benni means of a separate I/O address space (using specific I/O instructions) or
2154 095d0ed3 2024-10-05 benni by means of memory-mapped I/O (using general-purpose operand manipulation
2155 095d0ed3 2024-10-05 benni instructions).
2158 095d0ed3 2024-10-05 benni 2.5.1 I/O Address Space
2160 095d0ed3 2024-10-05 benni The 80286 provides a separate I/O address space, distinct from physical
2161 095d0ed3 2024-10-05 benni memory, to address the input/output ports that are used for external
2162 095d0ed3 2024-10-05 benni devices. The I/O address space consists of 2^(16) (64K) individually
2163 095d0ed3 2024-10-05 benni addressable 8-bit ports. Any two consecutive 8-bit ports can be treated as
2164 095d0ed3 2024-10-05 benni a 16-bit port. Thus, the I/O address space can accommodate up to 64K 8-bit
2165 095d0ed3 2024-10-05 benni ports or up to 32K 16-bit ports. I/O port addresses 00F8H to 00FFH are
2166 095d0ed3 2024-10-05 benni reserved by Intel.
2168 095d0ed3 2024-10-05 benni The 80286 can transfer either 8 or 16 bits at a time to a device located in
2169 095d0ed3 2024-10-05 benni the I/O space. Like words in memory, 16-bit ports should be aligned at
2170 095d0ed3 2024-10-05 benni even-numbered addresses so that the 16 bits will be transferred in a single
2171 095d0ed3 2024-10-05 benni access. An 8-bit port may be located at either an even or odd address. The
2172 095d0ed3 2024-10-05 benni internal registers in a given peripheral controller device should be
2173 095d0ed3 2024-10-05 benni assigned addresses as shown below.
2175 095d0ed3 2024-10-05 benni Port Register Port Addresses Example
2177 095d0ed3 2024-10-05 benni 16-bit even word addresses OUT FE,AX
2178 095d0ed3 2024-10-05 benni 8-bit; device on
2179 095d0ed3 2024-10-05 benni lower half of 16-bit
2181 095d0ed3 2024-10-05 benni data bus even byte addresses IN AL,FE
2183 095d0ed3 2024-10-05 benni 8-bit; device on upper
2184 095d0ed3 2024-10-05 benni half of 16-bit data bus odd byte addresses OUT FF,AL
2186 095d0ed3 2024-10-05 benni The I/O instructions IN and OUT (described in section 3.11.3) are provided
2187 095d0ed3 2024-10-05 benni to move data between I/O ports and the AX (16-bit I/O) or AL (8-bit I/O)
2188 095d0ed3 2024-10-05 benni general registers. The block I/O instructions INS and OUTS (described in
2189 095d0ed3 2024-10-05 benni section 4.1) move blocks of data between I/O ports and memory space (as
2190 095d0ed3 2024-10-05 benni shown below). In Protected Mode, an operating system may prevent a program
2191 095d0ed3 2024-10-05 benni from executing these I/O instructions. Otherwise, the function of the I/O
2192 095d0ed3 2024-10-05 benni instructions and the structure of the I/O space are identical for both modes
2193 095d0ed3 2024-10-05 benni of operation.
2195 095d0ed3 2024-10-05 benni INS es:byte ptr [di], DX
2196 095d0ed3 2024-10-05 benni OUTS DX, byte ptr [si]
2198 095d0ed3 2024-10-05 benni IN and OUT instructions address I/O with either a direct address to one of
2199 095d0ed3 2024-10-05 benni up to 256 port addresses, or indirectly via the DX register to one of up to
2200 095d0ed3 2024-10-05 benni 64K port addresses. Block I/O uses the DX register to specify the I/O
2201 095d0ed3 2024-10-05 benni address and either SI or DI to designate the source or destination memory
2202 095d0ed3 2024-10-05 benni address. For each transfer, SI or DI are either incremented or decremented
2203 095d0ed3 2024-10-05 benni as specified by the direction bit in the flag word while DX is constant to
2204 095d0ed3 2024-10-05 benni select the I/O device.
2207 095d0ed3 2024-10-05 benni 2.5.2 Memory-Mapped I/O
2209 095d0ed3 2024-10-05 benni I/O devices also may be placed in the 80286 memory address space. So long
2210 095d0ed3 2024-10-05 benni as the devices respond like memory components, they are indistinguishable to
2211 095d0ed3 2024-10-05 benni the processor.
2213 095d0ed3 2024-10-05 benni Memory-mapped I/O provides additional programming flexibility. Any
2214 095d0ed3 2024-10-05 benni instruction that references memory may be used to access an I/O port located
2215 095d0ed3 2024-10-05 benni in the memory space. For example, the MOV instruction can transfer data
2216 095d0ed3 2024-10-05 benni between any register and a port; and the AND, OR, and TEST instructions may
2217 095d0ed3 2024-10-05 benni be used to manipulate bits in the internal registers of a device (see
2218 095d0ed3 2024-10-05 benni figure 2-14). Memory-mapped I/O performed via the full instruction set
2219 095d0ed3 2024-10-05 benni maintains the full complement of addressing modes for selecting the desired
2220 095d0ed3 2024-10-05 benni I/O device.
2222 095d0ed3 2024-10-05 benni Memory-mapped I/O, like any other memory reference, is subject to access
2223 095d0ed3 2024-10-05 benni protection and control when executing in protected mode.
2226 095d0ed3 2024-10-05 benni Figure 2-14. Memory-Mapped I/O
2229 095d0ed3 2024-10-05 benni ADDRESS SPACE
2230 095d0ed3 2024-10-05 benni ╔════════════════╗ I/O DEVICE 1
2231 095d0ed3 2024-10-05 benni ║ ║ ╔═════════════════════╗
2232 095d0ed3 2024-10-05 benni ║ ║ ║ INTERNAL REGISTER ║
2233 095d0ed3 2024-10-05 benni ╟────────────────╢─ ── ─ ── ─ ── ─║─╔═════════════════╗ ║
2234 095d0ed3 2024-10-05 benni ║ ║ ║ ║ ║ ║
2235 095d0ed3 2024-10-05 benni ╟────────────────╢─ ── ─ ── ─ ── ─║─╚═════════════════╝ ║
2236 095d0ed3 2024-10-05 benni ║ ║ ╚═════════════════════╝
2238 095d0ed3 2024-10-05 benni ║ ║ I/O DEVICE 2
2239 095d0ed3 2024-10-05 benni ║ ║ ╔═════════════════════╗
2240 095d0ed3 2024-10-05 benni ║ ║ ║ INTERNAL REGISTER ║
2241 095d0ed3 2024-10-05 benni ║────────────────║─ ── ─ ── ─ ── ─║─╔═════════════════╗ ║
2242 095d0ed3 2024-10-05 benni ║ ║ ║ ║ ║ ║
2243 095d0ed3 2024-10-05 benni ║────────────────║─ ── ─ ── ─ ── ─║─╚═════════════════╝ ║
2244 095d0ed3 2024-10-05 benni ║ ║ ╚═════════════════════╝
2246 095d0ed3 2024-10-05 benni ╚════════════════╝
2249 095d0ed3 2024-10-05 benni 2.6 Interrupts and Exceptions
2251 095d0ed3 2024-10-05 benni The 80286 architecture supports several mechanisms for interrupting program
2252 095d0ed3 2024-10-05 benni execution. Internal interrupts are synchronous events that are the responses
2253 095d0ed3 2024-10-05 benni of the CPU to certain events detected during the execution of an
2254 095d0ed3 2024-10-05 benni instruction. External interrupts are asynchronous events typically
2255 095d0ed3 2024-10-05 benni triggered by external devices needing attention. The 80286 supports both
2256 095d0ed3 2024-10-05 benni maskable (controlled by the IF flag) and non-maskable interrupts. They cause
2257 095d0ed3 2024-10-05 benni the processor to temporarily suspend its present program execution in order
2258 095d0ed3 2024-10-05 benni to service the requesting device. The major distinction between these two
2259 095d0ed3 2024-10-05 benni kinds of interrupts is their origin: an internal interrupt is always
2260 095d0ed3 2024-10-05 benni reproducible by re-executing with the program and data that caused the
2261 095d0ed3 2024-10-05 benni interrupt, whereas an external interrupt is generally independent of the
2262 095d0ed3 2024-10-05 benni currently executing task.
2264 095d0ed3 2024-10-05 benni Interrupts 0-31 are reserved by Intel.
2266 095d0ed3 2024-10-05 benni Application programmers will normally not be concerned with servicing
2267 095d0ed3 2024-10-05 benni external interrupts. More information on external interrupts for system
2268 095d0ed3 2024-10-05 benni programmers may be found in Chapter 5, section 5.2, "Interrupt Handling for
2269 095d0ed3 2024-10-05 benni Real Address Mode," and in Chapter 9, "Interrupts, Traps and Faults for
2270 095d0ed3 2024-10-05 benni Protected Virtual Address Mode."
2272 095d0ed3 2024-10-05 benni In Real Address Mode, the application programmer is affected by two kinds
2273 095d0ed3 2024-10-05 benni of internal interrupts. (Internal interrupts are the result of executing an
2274 095d0ed3 2024-10-05 benni instruction which causes the interrupt.) One type of interrupt is called an
2275 095d0ed3 2024-10-05 benni exception because the interrupt only occurs if a particular fault condition
2276 095d0ed3 2024-10-05 benni exists. The other type of interrupt generates the interrupt every time the
2277 095d0ed3 2024-10-05 benni instruction is executed.
2279 095d0ed3 2024-10-05 benni The exceptions are: divide error, INTO detected overflow, bounds check,
2280 095d0ed3 2024-10-05 benni segment overrun, invalid operation code, and processor extension error (see
2281 095d0ed3 2024-10-05 benni table 2-4). A divide error exception results when the instructions DIV or
2282 095d0ed3 2024-10-05 benni IDIV are executed with a zero denominator; otherwise, the quotient will be
2283 095d0ed3 2024-10-05 benni too large for the destination operand (see section 3.3.4 for a discussion
2284 095d0ed3 2024-10-05 benni of DIV and IDIV). An overflow exception results when the INTO instruction is
2285 095d0ed3 2024-10-05 benni executed and the OF flag is set (after an arithmetic operation that set the
2286 095d0ed3 2024-10-05 benni overflow (OF) flag). (See section 3.6.3, "Software Generated Interrupts,"
2287 095d0ed3 2024-10-05 benni for a discussion of INTO.) A bounds check exception results when the BOUND
2288 095d0ed3 2024-10-05 benni instruction is executed and the array index it checks falls outside the
2289 095d0ed3 2024-10-05 benni bounds of the array. (See section 4.2 for a discussion of the BOUND
2290 095d0ed3 2024-10-05 benni instruction.) The segment overrun exception occurs when a word memory
2291 095d0ed3 2024-10-05 benni reference is attempted which extends beyond the end of a segment. An invalid
2292 095d0ed3 2024-10-05 benni operation code exception occurs if an attempt is made to execute an
2293 095d0ed3 2024-10-05 benni undefined instruction operation code. A processor extension error is
2294 095d0ed3 2024-10-05 benni generated when a processor extension detects an illegal operation. Refer to
2295 095d0ed3 2024-10-05 benni Chapter 5 for a more complete description of these exception conditions.
2297 095d0ed3 2024-10-05 benni The instruction INT generates an internal interrupt whenever it is
2298 095d0ed3 2024-10-05 benni executed. The effects of this interrupt (and the effects of all interrupts)
2299 095d0ed3 2024-10-05 benni is determined by the interrupt handler routines provided by the application
2300 095d0ed3 2024-10-05 benni program or as part of the system software (provided by system programmers).
2301 095d0ed3 2024-10-05 benni See Chapter 5 for more on this topic. The INT instruction itself is
2302 095d0ed3 2024-10-05 benni discussed in section 3.6.3.
2304 095d0ed3 2024-10-05 benni In Protected Mode, many more fault conditions are detected and result in
2305 095d0ed3 2024-10-05 benni internal interrupts. Protected Mode interrupts and faults are discussed in
2306 095d0ed3 2024-10-05 benni Chapter 9.
2309 095d0ed3 2024-10-05 benni 2.7 Hierarchy of Instruction Sets
2311 095d0ed3 2024-10-05 benni For descriptive purposes, the 80286 instruction set is partitioned into
2312 095d0ed3 2024-10-05 benni three distinct subsets: the Basic Instruction Set, the Extended Instruction
2313 095d0ed3 2024-10-05 benni Set, and the System Control Instruction Set. The "hierarchy" of instruction
2314 095d0ed3 2024-10-05 benni sets defined by this partitioning helps to clarify the relationships
2315 095d0ed3 2024-10-05 benni between the various processors in the 8086 family (see figure 2-15).
2317 095d0ed3 2024-10-05 benni The Basic Instruction Set, presented in Chapter 3, comprises the common
2318 095d0ed3 2024-10-05 benni subset of instructions found on all processors of the 8086 family. Included
2319 095d0ed3 2024-10-05 benni are instructions for logical and arithmetic operations, data movement,
2320 095d0ed3 2024-10-05 benni input/output, string manipulation, and transfer of control.
2322 095d0ed3 2024-10-05 benni The Extended Instruction Set, presented in Chapter 4, consists of those
2323 095d0ed3 2024-10-05 benni instructions found only on the 80186, 80188, and 80286 processors. Included
2324 095d0ed3 2024-10-05 benni are instructions for block structured procedure entry and exit, parameter
2325 095d0ed3 2024-10-05 benni validation, and block I/O transfers.
2327 095d0ed3 2024-10-05 benni The System Control Instruction Set, presented in Chapter 10, consists of
2328 095d0ed3 2024-10-05 benni those instructions unique to the 80286. These instructions control the
2329 095d0ed3 2024-10-05 benni memory management and protection mechanisms of the 80286.
2332 095d0ed3 2024-10-05 benni Table 2-4. 80286 Interrupt Vector Assignments (Real Address Mode)
2335 095d0ed3 2024-10-05 benni Function Interupt Related Return Address
2336 095d0ed3 2024-10-05 benni Number Instructions Before Instruction
2337 095d0ed3 2024-10-05 benni Causing Exception?
2338 095d0ed3 2024-10-05 benni Divide error exception 0 DIV, IDIV Yes
2339 095d0ed3 2024-10-05 benni Single step interrupt 1 All
2340 095d0ed3 2024-10-05 benni NMI interrupt 2 All
2341 095d0ed3 2024-10-05 benni Breakpoint interrupt 3 INT
2342 095d0ed3 2024-10-05 benni INTO detected overflow exception 4 INTO No
2343 095d0ed3 2024-10-05 benni BOUND range exceeded exception 5 BOUND Yes
2344 095d0ed3 2024-10-05 benni Invalid opcode exception 6 Any undefined Yes
2346 095d0ed3 2024-10-05 benni Processor extension 7 ESC or WAIT Yes
2347 095d0ed3 2024-10-05 benni not available exception
2348 095d0ed3 2024-10-05 benni Interrupt table limit 8 INT vector Yes
2349 095d0ed3 2024-10-05 benni too small exception is not within
2350 095d0ed3 2024-10-05 benni table limit
2351 095d0ed3 2024-10-05 benni Processor extension segment 9 ESC with memory No
2352 095d0ed3 2024-10-05 benni overrun interrupt operand extending
2353 095d0ed3 2024-10-05 benni beyond offset
2355 095d0ed3 2024-10-05 benni Reserved 10-12
2356 095d0ed3 2024-10-05 benni Segment overrun exception 13 Word memory Yes
2357 095d0ed3 2024-10-05 benni reference with
2358 095d0ed3 2024-10-05 benni offset = FFFF(H)
2359 095d0ed3 2024-10-05 benni or an attempt to
2360 095d0ed3 2024-10-05 benni execute past the
2361 095d0ed3 2024-10-05 benni end of a segment
2362 095d0ed3 2024-10-05 benni Reserved 14, 15
2363 095d0ed3 2024-10-05 benni Processor extension 16 ESC or WAIT
2364 095d0ed3 2024-10-05 benni error interrupt
2365 095d0ed3 2024-10-05 benni Reserved 17-31
2366 095d0ed3 2024-10-05 benni User defined 32-255
2370 095d0ed3 2024-10-05 benni Figure 2-15. Hierarchy of Instructions
2372 095d0ed3 2024-10-05 benni ╔══════════════════════╗
2375 095d0ed3 2024-10-05 benni ║ ╔════════════════╗ ║
2377 095d0ed3 2024-10-05 benni ║ ║ ╔══════════╗ ║ ║
2378 095d0ed3 2024-10-05 benni ║ ║ ║ 8086 ◄╫──╫──╫──BASIC INSTRUCTION SET
2379 095d0ed3 2024-10-05 benni ║ ║ ║ 8088 ║ ║ ║
2380 095d0ed3 2024-10-05 benni ║ ║ ╚══════════╝ ║ ║
2381 095d0ed3 2024-10-05 benni ║ ║ 80186 ◄───╫──╫──EXTENDED INSTRUCTION SET
2382 095d0ed3 2024-10-05 benni ║ ║ 80188 ║ ║
2383 095d0ed3 2024-10-05 benni ║ ╚════════════════╝ ║
2384 095d0ed3 2024-10-05 benni ║ 80286 ◄──────╫──SYSTEM CONTROL INSTRUCTION SET
2386 095d0ed3 2024-10-05 benni ╚══════════════════════╝
2389 095d0ed3 2024-10-05 benni Chapter 3 Basic Instruction Set
2391 095d0ed3 2024-10-05 benni ───────────────────────────────────────────────────────────────────────────
2393 095d0ed3 2024-10-05 benni The base architecture of the 80286 is identical to the complete instruction
2394 095d0ed3 2024-10-05 benni set of the 8086, 8088, 80188, and 80186 processors. The 80286 instruction
2395 095d0ed3 2024-10-05 benni set includes new forms of some instructions. These new forms reduce program
2396 095d0ed3 2024-10-05 benni size and improve the performance and ease of implementation of source code.
2398 095d0ed3 2024-10-05 benni This chapter describes the instructions which programmers can use to write
2399 095d0ed3 2024-10-05 benni application software for the 80286. The following chapters describe the
2400 095d0ed3 2024-10-05 benni operation of more complicated I/O and system control instructions.
2402 095d0ed3 2024-10-05 benni All instructions described in this chapter are available for both Real
2403 095d0ed3 2024-10-05 benni Address Mode and Protected Virtual Address Mode operation. The instruction
2404 095d0ed3 2024-10-05 benni descriptions note any differences that exist between the operation of an
2405 095d0ed3 2024-10-05 benni instruction in these two modes.
2407 095d0ed3 2024-10-05 benni This chapter also describes the operation of each application
2408 095d0ed3 2024-10-05 benni program-relative instruction and includes an example of using the
2409 095d0ed3 2024-10-05 benni instruction. The Instruction Dictionary in Appendix B contains formal
2410 095d0ed3 2024-10-05 benni descriptions of all instructions. Any opcode pattern that is not described
2411 095d0ed3 2024-10-05 benni in the Instruction Dictionary is undefined and results in an opcode
2412 095d0ed3 2024-10-05 benni violation trap (interrupt 6).
2415 095d0ed3 2024-10-05 benni 3.1 Data Movement Instructions
2417 095d0ed3 2024-10-05 benni These instructions provide convenient methods for moving bytes or words of
2418 095d0ed3 2024-10-05 benni data between memory and the registers of the base architecture.
2421 095d0ed3 2024-10-05 benni 3.1.1 General-Purpose Data Movement Instructions
2423 095d0ed3 2024-10-05 benni MOV (Move) transfers a byte or a word from the source operand to the
2424 095d0ed3 2024-10-05 benni destination operand. The MOV instruction is useful for transferring data to
2425 095d0ed3 2024-10-05 benni a register from memory, to memory from a register, between registers,
2426 095d0ed3 2024-10-05 benni immediate-to-register, or immediate-to-memory. Memory-to-memory or segment
2427 095d0ed3 2024-10-05 benni register-to-segment register moves are not allowed.
2430 095d0ed3 2024-10-05 benni MOV DS,AX. Replaces the contents of register DS with the contents of
2431 095d0ed3 2024-10-05 benni register AX.
2433 095d0ed3 2024-10-05 benni XCHG (Exchange) swaps the contents of two operands. This instruction takes
2434 095d0ed3 2024-10-05 benni the place of three MOV instructions. It does not require a temporary memory
2435 095d0ed3 2024-10-05 benni location to save the contents of one operand while you load the other.
2437 095d0ed3 2024-10-05 benni The XCHG instruction can swap two byte operands or two word operands, but
2438 095d0ed3 2024-10-05 benni not a byte for a word or a word for a byte. The operands for the XCHG
2439 095d0ed3 2024-10-05 benni instruction may be two register operands, or a register operand with a
2440 095d0ed3 2024-10-05 benni memory operand. When used with a memory operand, XCHG automatically
2441 095d0ed3 2024-10-05 benni activates the LOCK signal.
2444 095d0ed3 2024-10-05 benni XCHG BX,WORDOPRND. Swaps the contents of register BX with the contents
2445 095d0ed3 2024-10-05 benni of the memory word identified by the label WORDOPRND after asserting
2446 095d0ed3 2024-10-05 benni bus lock.
2449 095d0ed3 2024-10-05 benni 3.1.2 Stack Manipulation Instructions
2451 095d0ed3 2024-10-05 benni PUSH (Push) decrements the stack pointer (SP) by two and then transfers a
2452 095d0ed3 2024-10-05 benni word from the source operand to the top of stack indicated by SP. See figure
2453 095d0ed3 2024-10-05 benni 3-1. PUSH is often used to place parameters on the stack before calling a
2454 095d0ed3 2024-10-05 benni procedure; it is also the basic means of storing temporary variables on the
2455 095d0ed3 2024-10-05 benni stack. The PUSH instruction operates on memory operands, immediate operands
2456 095d0ed3 2024-10-05 benni (new with the 80286), and register operands (including segment registers).
2459 095d0ed3 2024-10-05 benni PUSH WORDOPRND. Transfers a 16-bit value from the memory word identified
2460 095d0ed3 2024-10-05 benni by the label WORDOPRND to the memory location which represents the current
2461 095d0ed3 2024-10-05 benni top of stack (byte transfers are not allowed).
2463 095d0ed3 2024-10-05 benni PUSHA (Push All Registers) saves the contents of the eight general
2464 095d0ed3 2024-10-05 benni registers on the stack. See figure 3-2. This instruction simplifies
2465 095d0ed3 2024-10-05 benni procedure calls by reducing the number of instructions required to retain
2466 095d0ed3 2024-10-05 benni the contents of the general registers for use in a procedure. PUSHA is
2467 095d0ed3 2024-10-05 benni complemented by POPA (see below).
2469 095d0ed3 2024-10-05 benni The processor pushes the general registers on the stack in the following
2470 095d0ed3 2024-10-05 benni order: AX, CX, DX, BX, the initial value of SP before AX was pushed, BP, SI,
2474 095d0ed3 2024-10-05 benni PUSHA. Pushes onto the stack the contents of the eight general registers.
2476 095d0ed3 2024-10-05 benni POP (Pop) transfers the word at the current top of stack (indicated by SP)
2477 095d0ed3 2024-10-05 benni to the destination operand, and then increments SP by two to point to the
2478 095d0ed3 2024-10-05 benni new top of stack. See figure 3-3. POP moves information from the stack to
2479 095d0ed3 2024-10-05 benni either a register or memory. The only restriction on POP is that it cannot
2480 095d0ed3 2024-10-05 benni place a value in register CS.
2483 095d0ed3 2024-10-05 benni POP BX. Replaces the contents of register BX with the contents of the
2484 095d0ed3 2024-10-05 benni memory location at the top of stack.
2486 095d0ed3 2024-10-05 benni POPA (Pop All Registers) restores the registers saved on the stack by
2487 095d0ed3 2024-10-05 benni PUSHA, except that it ignores the value of SP. See figure 3-4.
2490 095d0ed3 2024-10-05 benni POPA. Pops from the stack the saved contents of the general registers,
2491 095d0ed3 2024-10-05 benni and restores the registers (except SP) to their original state.
2494 095d0ed3 2024-10-05 benni Figure 3-1. PUSH
2497 095d0ed3 2024-10-05 benni HIGH ADDRESS ║ ║ ║ ║
2498 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ SS LIMIT
2499 095d0ed3 2024-10-05 benni OPERANDS FROM ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2500 095d0ed3 2024-10-05 benni PREVIOUS PUSH ╠═══════════════╣ ╠═══════════════╣
2501 095d0ed3 2024-10-05 benni INSTRUCTIONS SP─►║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2502 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ SP ALWAYS POINTS
2503 095d0ed3 2024-10-05 benni ║ ║ ║ OPERAND ║◄─TO THE LAST WORD
2504 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ PUSHED ONTO THE
2505 095d0ed3 2024-10-05 benni ║ ║ ║ ║ STACK (TOS)
2506 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2508 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2509 095d0ed3 2024-10-05 benni ║ ║ ║ ║ SS ALWAYS POINTS
2510 095d0ed3 2024-10-05 benni LOW ADDRESS ╠═══════════════╣ ╠═══════════════╣ TO LOWEST ADDRESS
2511 095d0ed3 2024-10-05 benni ║ ║ ║ ║ USED BY THE STACK
2512 095d0ed3 2024-10-05 benni • BEFORE • • AFTER •
2513 095d0ed3 2024-10-05 benni PUSH OPERAND PUSH OPERAND
2515 095d0ed3 2024-10-05 benni PUSH decrements SP by 2 bytes and places the operand in the stack at the
2516 095d0ed3 2024-10-05 benni location to which SP points.
2519 095d0ed3 2024-10-05 benni Figure 3-2. PUSHA
2522 095d0ed3 2024-10-05 benni HIGH ADDRESS ║ ║ ║ ║
2523 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ SS LIMIT
2524 095d0ed3 2024-10-05 benni OPERANDS FROM ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2525 095d0ed3 2024-10-05 benni PREVIOUS PUSH ╠═══════════════╣ ╠═══════════════╣
2526 095d0ed3 2024-10-05 benni INSTRUCTIONS ┌──►║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2527 095d0ed3 2024-10-05 benni │ ╠═══════════════╣ ╠═══════════════╣
2528 095d0ed3 2024-10-05 benni SP──┘ ║ ║ ║ AX ║
2529 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2530 095d0ed3 2024-10-05 benni ║ ║ ║ CX ║
2531 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2532 095d0ed3 2024-10-05 benni ║ ║ ║ DX ║
2533 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2534 095d0ed3 2024-10-05 benni ║ ║ ║ BX ║
2535 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2536 095d0ed3 2024-10-05 benni ║ ║ ║ OLD SP ║
2537 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2538 095d0ed3 2024-10-05 benni ║ ║ ║ BP ║
2539 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2540 095d0ed3 2024-10-05 benni ║ ║ ║ SI ║
2541 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2542 095d0ed3 2024-10-05 benni ║ ║ ║ DI ║◄───SP
2543 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2545 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2547 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2549 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2551 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2553 095d0ed3 2024-10-05 benni LOW ADDRESS ╠═══════════════╣ ╠═══════════════╣ SS
2556 095d0ed3 2024-10-05 benni BEFORE AFTER
2557 095d0ed3 2024-10-05 benni PUSHA PUSHA
2559 095d0ed3 2024-10-05 benni PUSHA copies the contents of the eight general registers to the stack in
2560 095d0ed3 2024-10-05 benni the above order. The instruction decrements SP by 16 bytes (8 words) to
2561 095d0ed3 2024-10-05 benni point to the last word pushed on the stack.
2564 095d0ed3 2024-10-05 benni Figure 3-3. POP
2567 095d0ed3 2024-10-05 benni HIGH ADDRESS ║ ║ ║ ║
2568 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ SS LIMIT
2569 095d0ed3 2024-10-05 benni OPERANDS FROM ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2570 095d0ed3 2024-10-05 benni PREVIOUS PUSH ╠═══════════════╣ ╠═══════════════╣
2571 095d0ed3 2024-10-05 benni INSTRUCTIONS ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║◄───SP
2572 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2573 095d0ed3 2024-10-05 benni SP───►║ OPERAND ║ ║ ║
2574 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2576 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2578 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2580 095d0ed3 2024-10-05 benni LOW ADDRESS ╠═══════════════╣ ╠═══════════════╣ SS
2582 095d0ed3 2024-10-05 benni • BEFORE • • AFTER •
2583 095d0ed3 2024-10-05 benni POP OPERAND POP OPERAND
2585 095d0ed3 2024-10-05 benni POP copies the contents of the stack location before SP to the operand in
2586 095d0ed3 2024-10-05 benni the instruction. POP then increments SP by 2 bytes (1 word).
2588 095d0ed3 2024-10-05 benni Figure 3-4. POPA
2591 095d0ed3 2024-10-05 benni HIGH ADDRESS ║ ║ ║ ║
2592 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣ SS LIMIT
2593 095d0ed3 2024-10-05 benni OPERANDS FROM ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║
2594 095d0ed3 2024-10-05 benni PREVIOUS PUSH ╠═══════════════╣ ╠═══════════════╣
2595 095d0ed3 2024-10-05 benni INSTRUCTIONS ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║ ║▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒║◄───SP
2596 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2597 095d0ed3 2024-10-05 benni ║ AX ║ ║ ║
2598 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2599 095d0ed3 2024-10-05 benni ║ CX ║ ║ ║
2600 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2601 095d0ed3 2024-10-05 benni ║ DX ║ ║ ║
2602 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2603 095d0ed3 2024-10-05 benni ║ BX ║ ║ ║
2604 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2605 095d0ed3 2024-10-05 benni ║ SP ║ ║ ║
2606 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2607 095d0ed3 2024-10-05 benni ║ BP ║ ║ ║
2608 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2609 095d0ed3 2024-10-05 benni ║ SI ║ ║ ║
2610 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2611 095d0ed3 2024-10-05 benni SP───►║ DI ║ ║ ║
2612 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2614 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2616 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2618 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2620 095d0ed3 2024-10-05 benni ╠═══════════════╣ ╠═══════════════╣
2622 095d0ed3 2024-10-05 benni LOW ADDRESS ╠═══════════════╣ ╠═══════════════╣ SS
2623 095d0ed3 2024-10-05 benni • BEFORE • • AFTER •
2624 095d0ed3 2024-10-05 benni POPA POPA
2626 095d0ed3 2024-10-05 benni POPA copies the contents of seven stack locations to the corresponding
2627 095d0ed3 2024-10-05 benni general registers. POPA discards the stored value of SP.
2630 095d0ed3 2024-10-05 benni 3.2 Flag Operation With the Basic Instruction Set
2633 095d0ed3 2024-10-05 benni 3.2.1 Status Flags
2635 095d0ed3 2024-10-05 benni The status flags of the FLAGS register reflect conditions that result from
2636 095d0ed3 2024-10-05 benni a previous instruction or instructions. The arithmetic instructions use OF,
2637 095d0ed3 2024-10-05 benni SF, ZF, AF, PF, and CF.
2639 095d0ed3 2024-10-05 benni The SCAS (Scan String), CMPS (Compare String), and LOOP instructions use ZF
2640 095d0ed3 2024-10-05 benni to signal that their operations are complete. The base architecture includes
2641 095d0ed3 2024-10-05 benni instructions to set, clear, and complement CF before execution of an
2642 095d0ed3 2024-10-05 benni arithmetic instruction. See figure 3-5 and tables 3-1 and 3-2.
2645 095d0ed3 2024-10-05 benni 3.2.2 Control Flags
2647 095d0ed3 2024-10-05 benni The control flags of the FLAGS register determine processor operations for
2648 095d0ed3 2024-10-05 benni string instructions, maskable interrupts, and debugging.
2650 095d0ed3 2024-10-05 benni Setting DF (direction flag) causes string instructions to auto-decrement;
2651 095d0ed3 2024-10-05 benni that is, to process strings from high addresses to low addresses, or from
2652 095d0ed3 2024-10-05 benni "right-to-left." Clearing DF causes string instructions to auto-increment,
2653 095d0ed3 2024-10-05 benni or to process strings from "left-to-right."
2655 095d0ed3 2024-10-05 benni Setting IF (interrupt flag) allows the CPU to recognize external (maskable)
2656 095d0ed3 2024-10-05 benni interrupt requests. Clearing IF disables these interrupts. IF has no effect
2657 095d0ed3 2024-10-05 benni on either internally generated interrupts, nonmaskable external interrupts,
2658 095d0ed3 2024-10-05 benni or processor extension segment overrun interrupts.
2660 095d0ed3 2024-10-05 benni Setting TF (trap flag) puts the processor into single-step mode for
2661 095d0ed3 2024-10-05 benni debugging. In this mode, the CPU automatically generates an internal
2662 095d0ed3 2024-10-05 benni interrupt after each instruction, allowing a program to be inspected as it
2663 095d0ed3 2024-10-05 benni executes each instruction, instruction by instruction.
2666 095d0ed3 2024-10-05 benni Table 3-1. Status Flags' Functions
2668 095d0ed3 2024-10-05 benni Bit Position Name Function
2670 095d0ed3 2024-10-05 benni 0 CF Carry Flag--Set on high-order bit carry or borrow;
2671 095d0ed3 2024-10-05 benni cleared otherwise
2673 095d0ed3 2024-10-05 benni 2 PF Parity Flag--Set if low-order eight bits of result
2674 095d0ed3 2024-10-05 benni contain an even number of 1 bits; cleared otherwise
2676 095d0ed3 2024-10-05 benni 4 AF Set on carry from or borrow to the low order four
2677 095d0ed3 2024-10-05 benni bits of AL; cleared otherwise
2679 095d0ed3 2024-10-05 benni 6 ZF Zero Flag--Set if result is zero; cleared otherwise
2681 095d0ed3 2024-10-05 benni 7 SF Sign Flag--Set equal to high-order bit of result (0
2682 095d0ed3 2024-10-05 benni if positive, 1 if negative)
2684 095d0ed3 2024-10-05 benni 11 OF Overflow Flag--Set if result is too-large a positive
2685 095d0ed3 2024-10-05 benni number or too-small a negative number (excluding
2686 095d0ed3 2024-10-05 benni sign-bit) to fit in destination operand; cleared
2687 095d0ed3 2024-10-05 benni otherwise
2690 095d0ed3 2024-10-05 benni Table 3-2. Control Flags' Functions
2692 095d0ed3 2024-10-05 benni Bit Position Name Function
2694 095d0ed3 2024-10-05 benni 8 TF Trap (Single Step) Flag--Once set, a single step
2695 095d0ed3 2024-10-05 benni interrupt occurs after the next instruction executes.
2696 095d0ed3 2024-10-05 benni TF is cleared by the single step interrupt.
2698 095d0ed3 2024-10-05 benni 9 IF Interrupt-enable Flag--When set, maskable interrupts
2699 095d0ed3 2024-10-05 benni will cause the CPU to transfer control to an interrupt
2700 095d0ed3 2024-10-05 benni vector-specified location.
2702 095d0ed3 2024-10-05 benni 10 DF Direction Flag--Causes string instructions to auto
2703 095d0ed3 2024-10-05 benni decrement the appropriate index registers when set.
2704 095d0ed3 2024-10-05 benni Clearing DF causes auto increment.
2707 095d0ed3 2024-10-05 benni Figure 3-5. Flag Word Contents
2709 095d0ed3 2024-10-05 benni STATUS FLAGS:
2710 095d0ed3 2024-10-05 benni CARRY────────────────────────────────────────────────┐
2711 095d0ed3 2024-10-05 benni PARITY─────────────────────────────────────────┐ │
2712 095d0ed3 2024-10-05 benni AUXILLIARY CARRY─────────────────────────┐ │ │
2713 095d0ed3 2024-10-05 benni ZERO───────────────────────────────┐ │ │ │
2714 095d0ed3 2024-10-05 benni SIGN────────────────────────────┐ │ │ │ │
2715 095d0ed3 2024-10-05 benni OVERFLOW────────────┐ │ │ │ │ │
2716 095d0ed3 2024-10-05 benni │ │ │ │ │ │
2717 095d0ed3 2024-10-05 benni 15 14 13 12▼11 10 9 8▼ 7▼ 6 5▼ 4 3▼ 2 1▼ 0
2718 095d0ed3 2024-10-05 benni ╔══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╤══╗
2719 095d0ed3 2024-10-05 benni FLAGS:║▒▒│NT│IOPL │OF│DF│IF│TF│SF│ZF│▒▒│AF│▒▒│PF│▒▒│CF║
2720 095d0ed3 2024-10-05 benni ╚══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╧══╝
2721 095d0ed3 2024-10-05 benni ▲ ▲ ▲ ▲ ▲
2722 095d0ed3 2024-10-05 benni │ │ │ │ │ CONTROL FLAGS:
2723 095d0ed3 2024-10-05 benni │ │ │ │ └───────────TRAP FLAG
2724 095d0ed3 2024-10-05 benni │ │ │ └──────────────INTERRUPT ENABLE
2725 095d0ed3 2024-10-05 benni │ │ └─────────────────DIRECTION FLAG
2726 095d0ed3 2024-10-05 benni │ │ SPECIAL FIELDS:
2727 095d0ed3 2024-10-05 benni │ └─────────────────────────I/O PRIVILEGE LEVEL
2728 095d0ed3 2024-10-05 benni └─────────────────────────────NESTED TASK FLAG
2731 095d0ed3 2024-10-05 benni 3.3 Arithmetic Instructions
2733 095d0ed3 2024-10-05 benni The arithmetic instructions of the 8086-family processors simplify the
2734 095d0ed3 2024-10-05 benni manipulation of numerical data. Multiplication and division instructions
2735 095d0ed3 2024-10-05 benni ease the handling of signed and unsigned binary integers as well as unpacked
2736 095d0ed3 2024-10-05 benni decimal integers.
2738 095d0ed3 2024-10-05 benni An arithmetic operation may consist of two register operands, a general
2739 095d0ed3 2024-10-05 benni register source operand with a memory destination operand, a memory source
2740 095d0ed3 2024-10-05 benni operand with a register destination operand, or an immediate field with
2741 095d0ed3 2024-10-05 benni either a register or memory destination operand, but not two memory
2742 095d0ed3 2024-10-05 benni operands. Arithmetic instructions can operate on either byte or word
2743 095d0ed3 2024-10-05 benni operands.
2746 095d0ed3 2024-10-05 benni 3.3.1 Addition Instructions
2748 095d0ed3 2024-10-05 benni ADD (Add Integers) replaces the destination operand with the sum of the
2749 095d0ed3 2024-10-05 benni source and destination operands. ADD affects OF, SF, AF, PF, CF, and ZF.
2752 095d0ed3 2024-10-05 benni ADD BL, BYTEOPRND. Adds the contents of the memory byte labeled
2753 095d0ed3 2024-10-05 benni BYTEOPRND to the contents of BL, and replaces BL with the resulting sum.
2755 095d0ed3 2024-10-05 benni ADC (Add Integers with Carry) sums the operands, adds one if CF is set, and
2756 095d0ed3 2024-10-05 benni replaces the destination operand with the result. ADC can be used to add
2757 095d0ed3 2024-10-05 benni numbers longer than 16 bits. ADC affects OF, SF, AF, PF, CF, and ZF.
2760 095d0ed3 2024-10-05 benni ADC BX, CX. Replaces the contents of the destination operand BX with
2761 095d0ed3 2024-10-05 benni the sum of BX, CS, and 1 (if CF is set). If CF is cleared, ADC
2762 095d0ed3 2024-10-05 benni performs the same operation as the ADD instruction.
2764 095d0ed3 2024-10-05 benni INC (Increment) adds one to the destination operand. The processor treats
2765 095d0ed3 2024-10-05 benni the operand as an unsigned binary number. INC updates AF, OF, PF, SF, and
2766 095d0ed3 2024-10-05 benni ZF, but it does not affect CF. Use ADD with an immediate value of 1 if an
2767 095d0ed3 2024-10-05 benni increment that updates carry (CF) is needed.
2770 095d0ed3 2024-10-05 benni INC BL. Adds 1 to the contents of BL.
2773 095d0ed3 2024-10-05 benni 3.3.2 Subtraction Instructions
2775 095d0ed3 2024-10-05 benni SUB (Subtract Integers) subtracts the source operand from the destination
2776 095d0ed3 2024-10-05 benni operand and replaces the destination operand with the result. If a borrow is
2777 095d0ed3 2024-10-05 benni required, carry flag is set. The operands may be signed or unsigned bytes or
2778 095d0ed3 2024-10-05 benni words. SUB affects OF, SF, ZF, AF, PF, and CF.
2781 095d0ed3 2024-10-05 benni SUB WORDOPRND, AX. Replaces the contents of the destination operand
2782 095d0ed3 2024-10-05 benni WORDOPRND with the result obtained by subtracting the contents of AX from
2783 095d0ed3 2024-10-05 benni the contents of the memory word labeled WORDOPRND.
2785 095d0ed3 2024-10-05 benni SBB (Subtract Integers with Borrow) subtracts the source operand from the
2786 095d0ed3 2024-10-05 benni destination operand, subtracts 1 if CF is set, and returns the result to the
2787 095d0ed3 2024-10-05 benni destination operand. The operands may be signed or unsigned bytes or words.
2788 095d0ed3 2024-10-05 benni SBB may be used to subtract numbers longer than 16 bits. This instruction
2789 095d0ed3 2024-10-05 benni affects OF, SF, ZF, AF, PF, and CF. The carry flag is set if a borrow is
2790 095d0ed3 2024-10-05 benni required.
2793 095d0ed3 2024-10-05 benni SBB BL, 32. Subtracts 32 from the contents of BL and then decrements the
2794 095d0ed3 2024-10-05 benni result of this subtraction by one if CF is set. If CF is cleared, SBB
2795 095d0ed3 2024-10-05 benni performs the same operation as SUB.
2797 095d0ed3 2024-10-05 benni DEC (Decrement) subtracts 1 from the destination operand. DEC updates AF,
2798 095d0ed3 2024-10-05 benni OF, PF, SF, and ZF, but it does not affect CF. Use SUB with an immediate
2799 095d0ed3 2024-10-05 benni value of 1 to perform a decrement that affects carry.
2802 095d0ed3 2024-10-05 benni DEC BX. Subtracts 1 from the contents of BX and places the result back in
2806 095d0ed3 2024-10-05 benni 3.3.3 Multiplication Instructions
2808 095d0ed3 2024-10-05 benni MUL (Unsigned Integer Multiply) performs an unsigned multiplication of the
2809 095d0ed3 2024-10-05 benni source operand and the accumulator. If the source is a byte, the processor
2810 095d0ed3 2024-10-05 benni multiplies it by the contents of AL and returns the double-length result to
2811 095d0ed3 2024-10-05 benni AH and AL.
2813 095d0ed3 2024-10-05 benni If the source operand is a word, the processor multiplies it by the
2814 095d0ed3 2024-10-05 benni contents of AX and returns the double-length result to DX and AX. MUL sets
2815 095d0ed3 2024-10-05 benni CF and OF to indicate that the upper half of the result is nonzero;
2816 095d0ed3 2024-10-05 benni otherwise, they are cleared. This instruction leaves SF, ZF, AF, and PF
2817 095d0ed3 2024-10-05 benni undefined.
